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AD7839AS

Part # AD7839AS
Description DAC 8-CH R-2R 13-bit 44-Pin MQFP
Category IC
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Analog Devices
Date Code: 0024
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD7839
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1999
Octal 13-Bit, Parallel Input,
Voltage-Output DAC
FUNCTIONAL BLOCK DIAGRAM
DAC
REG
A
INPUT
REG
A
13
DAC E
AD7839
DB12
DB0
WR
CS
A0
A1
A2
LDAC
RR
RR
R
R
R
R
R
R
R
R
R
R
R
R
13 13
DAC
REG
B
INPUT
REG
B
13 13
13
DAC
REG
C
INPUT
REG
C
13 13
13
DAC
REG
D
INPUT
REG
D
13 13
13
DAC
REG
E
INPUT
REG
E
13 13
13
DAC
REG
F
INPUT
REG
F
13 13
13
DAC
REG
G
INPUT
REG
G
13 13
13
DAC
REG
H
INPUT
REG
H
13 13
13
DAC D
DAC C
DAC F
DAC B
DAC A
DAC G
DAC H
V
CC
V
SS
V
DD
V
REF
(+)
AB
V
REF
(–)
AB
DUTGND
CD
DUTGND
AB
V
OUT
A
V
OUT
B
V
OUT
C
V
OUT
D
V
OUT
E
V
OUT
F
V
OUT
G
V
OUT
H
DUTGND
GH
DUTGND
EF
V
REF
(–)
CDEF
V
REF
(+)
CDEF
V
REF
(–)
GH
V
REF
(+)
GH
GND
CLR
ADDRESS
DECODE
FEATURES
Eight 13-Bit DACs in One Package
Voltage Outputs
Offset Adjust for Each DAC Pair
Reference Range of 5 V
Maximum Output Voltage Range of 10 V
Clear Function to User-Defined Voltage
44-Lead MQFP Package
APPLICATIONS
Automatic Test Equipment
Process Control
General Purpose Instrumentation
GENERAL DESCRIPTION
The AD7839 contains eight 13-bit DACs on one monolithic
chip. It has output voltages with a full-scale range of ±10 V
from reference voltages of ±5 V.
The AD7839 accepts 13-bit parallel loaded data from the exter-
nal bus into one of the input registers under the control of the
WR, CS and DAC channel address pins, A0–A2.
The DAC outputs are updated on reception of new data into
the DAC registers. All the outputs may be updated simulta-
neously by taking the LDAC input low.
Each DAC output is buffered with a gain-of-two amplifier into
which an external DAC offset voltage can be inserted via the
DUTGNDx pins.
The AD7839 is available in a 44-lead MQFP package.
–2–
REV. 0
AD7839–SPECIFICATIONS
(V
CC
= +5 V 5%; V
DD
= +15 V 5%; V
SS
= –15 V 5%; GND = DUTGND = 0 V;
R
L
= 5 k and C
L
= 50 pF to GND, T
A
1
= T
MIN
to T
MAX
, unless otherwise noted.)
Parameter A Version Units Test Conditions/Comments
ACCURACY
Resolution 13 Bits
Relative Accuracy ±2 LSB max Typically ±0.5 LSB
Differential Nonlinearity ±0.9 LSB max Guaranteed Monotonic Over Temperature
Zero-Scale Error ±4LSB maxV
REF
(+) = +5 V, V
REF
(–) = –5 V. Typically within ±1 LSB
Full-Scale Error ±4LSB maxV
REF
(+) = +5 V, V
REF
(–) = –5 V. Typically within ±1 LSB
Gain Error ±1 LSB typ V
REF
(+) = +5 V, V
REF
(–) = –5 V
Gain Temperature Coefficient
2
0.5 ppm FSR/°C typ
10 ppm FSR/°C max
DC Crosstalk
2
120 µV max See Terminology. Typically 75 µV
REFERENCE INPUTS
2
DC Input Impedance 100 M typ
Input Current ±1 µA max Per Input. Typically ±0.03 µA
V
REF
(+) Range 0/+5 V min/max
V
REF
(–) Range –5/0 V min/max
[V
REF
(+) – V
REF
(–)] +2/+10 V min/max For Specified Performance. Can Go as Low as 0 V, but
Performance Not Guaranteed
DUTGND INPUTS
2
DC Input Impedance 60 k typ
Max Input Current ±0.3 mA typ Per Input
Input Range –2/+2 V min/max
OUTPUT CHARACTERISTICS
2
Output Voltage Swing ± 10 V min 2 × (V
REF
(–) + [V
REF
(+) – V
REF
(–)] × D) – V
DUTGND
Short Circuit Current 15 mA max
Resistive Load 5 k min To 0 V
Capacitive Load 50 pF max To 0 V
DC Output Impedance 0.5 max
DIGITAL INPUTS
2
V
INH
, Input High Voltage 2.4 V min
V
INL
, Input Low Voltage 0.8 V max
I
INH
, Input Current Total for All Pins
@ +25°C1µA max
T
MIN
to T
MAX
±10 µA max
C
IN
, Input Capacitance 10 pF max
POWER REQUIREMENTS
3
V
CC
+4.75/+5.25 V min/max For Specified Performance
V
DD
+14.25/+15.75 V min/max For Specified Performance
V
SS
–14.25/–15.75 V min/max For Specified Performance
Power Supply Sensitivity
2
␣␣ Full Scale/V
DD
90 dB typ
␣␣ Full Scale/V
SS
90 dB typ
I
CC
0.5 mA max V
INH
= V
CC
, V
INL
= GND. Dynamic Current
I
DD
10 mA max Outputs Unloaded. Typically 8 mA
I
SS
10 mA max Outputs Unloaded. Typically 8 mA
NOTES
1
Temperature range for A Version: –40°C to +85°C
2
Guaranteed by characterization. Not production tested.
3
The AD7839 is functional with power supplies of ± 12 V ± 10% with reduced output range. At 12 V it is recommended to restrict reference range to ± 4 V due to
output amplifier headroom limitations
Specifications subject to change without notice.
–3–REV. 0
AD7839
(These characteristics are included for Design Guidance and are not subject
to production testing.)
AC PERFORMANCE CHARACTERISTICS
Parameter A Units Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Voltage Settling Time 30 µs typ Full-Scale Change to ±1/2 LSB. DAC Latch Contents Alternately
40 µs max Loaded with All 0s and All 1s
Slew Rate 0.7 V/µs typ
Digital-to-Analog Glitch Impulse 230 nV-s typ Measured with V
REF
(+) = +5 V, V
REF
(–) = –5 V. DAC Latch
Alternately Loaded with 0FFF Hex and 1000 Hex. Not Dependent
on Load Conditions
Channel-to-Channel Isolation 99 dB typ See Terminology
DAC-to-DAC Crosstalk 40 nV-s typ See Terminology
Digital Crosstalk 0.2 nV-s typ Feedthrough to DAC Output Under Test Due to Change in Digital
Input Code to Another Converter
Digital Feedthrough 0.1 nV-s typ Effect of Input Bus Activity on DAC Output Under Test
Output Noise Spectral Density
␣ ␣ @ 1 kHz 200 nV/Hz
typ All 1s Loaded to DAC. V
REF
(+) = V
REF
(–) = 0 V
Specifications subject to change without notice.
TIMING SPECIFICATIONS
1, 2
Parameter Limit at T
MIN,
T
MAX
Units Description
t
1
15 ns min Address to WR Setup Time
t
2
0 ns min Address to WR Hold Time
t
3
50 ns min CS Pulsewidth Low
t
4
50 ns min WR Pulsewidth Low
t
5
0 ns min CS to WR Setup Time
t
6
0 ns min WR to CS Hold Time
t
7
20 ns min Data Setup Time
t
8
0 ns min Data Hold Time
t
9
30 µs typ Settling Time
t
10
300 ns max CLR Pulse Activation Time
t
11
50 ns min LDAC Pulsewidth Low
NOTES
1
All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
Rise and fall times should be no longer than 50 ns.
Specifications subject to change without notice.
t
1
t
2
t
5
t
6
t
3
t
4
t
7
t
8
t
9
t
10
LDAC
CLR
WR
CS
A0, A1, A2
DATA
V
OUT
V
OUT
t
11
Figure 1. Timing Diagram
(V
CC
= +5 V 5%; V
DD
= +15 V 5%; V
SS
= –15 V 5%; GND = DUTGND = 0 V)
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