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AD7837BR

Part # AD7837BR
Description IC DAC 12BIT DUAL MULT 24-SOIC
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
LC
2
MOS
Complete, Dual 12-Bit MDACs
AD7837/AD7847
FUNCTIONAL BLOCK DIAGRAMS
LS INPUT
LATCH
CONTROL
LOGIC
AGNDA
MS INPUT
LATCH
DAC LATCH A
DAC A
48
12
LDAC
A1
A0
CS
WR
R
FBA
V
OUTA
AD7837
DGND
DAC B
12
DAC LATCH B
48
LS INPUT
LATCH
MS INPUT
LATCH
AGNDB
R
FBB
V
OUTB
V
SS
V
DD
V
REFA
V
REFB
DB0
DB7
CONTROL
LOGIC
AGNDA
DAC LATCH A
DAC A
CSB
CSA
WR
V
OUTA
AD7847
DGND
DAC B
DAC LATCH B
AGNDB
V
OUTB
V
SS
V
DD
V
REFA
V
REFB
DB0
DB11
GENERAL DESCRIPTION
The AD7837/AD7847 is a complete, dual, 12-bit multiplying
digital-to-analog converter with output amplifiers on a mono-
lithic CMOS chip. No external user trims are required to
achieve full specified performance.
Both parts are microprocessor compatible, with high speed data
latches and interface logic. The AD7847 accepts 12-bit parallel
data which is loaded into the respective DAC latch using the
WR input and a separate Chip Select input for each DAC. The
AD7837 has a double-buffered 8-bit bus interface structure
with data loaded to the respective input latch in two write opera-
tions. An asynchronous LDAC signal on the AD7837 updates
the DAC latches and analog outputs.
The output amplifiers are capable of developing ±10 V across a
2 k load. They are internally compensated with low input off-
set voltage due to laser trimming at wafer level.
The amplifier feedback resistors are internally connected to
V
OUT
on the AD7847.
The AD7837/AD7847 is fabricated in Linear Compatible CMOS
(LC
2
MOS), an advanced, mixed technology process that com-
bines precision bipolar circuits with low power CMOS logic.
A novel low leakage configuration (U.S. Patent No. 4,590,456)
ensures low offset errors over the specified temperature range.
PRODUCT HIGHLIGHTS
1. The AD7837/AD7847 is a dual, 12-bit, voltage-out MDAC
on a single chip. This single chip design offers considerable
space saving and increased reliability over multichip designs.
2. The AD7837 and the AD7847 provide a fast versatile inter-
face to 8-bit or 16-bit data bus structures.
FEATURES
Two 12-Bit MDACs with Output Amplifiers
4-Quadrant Multiplication
Space-Saving 0.3", 24-Lead DIP and 24-Terminal
SOIC Package
Parallel Loading Structure: AD7847
(8 + 4) Loading Structure: AD7837
APPLICATIONS
Automatic Test Equipment
Function Generation
Waveform Reconstruction
Programmable Power Supplies
Synchro Applications
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2000
REV. C
–2–
AD7837/AD7847–SPECIFICATIONS
1
(V
DD
= +15 V 5%, V
SS
= –15 V 5%, AGNDA = AGNDB = DGND
= O V. V
REFA
= V
REFB
= +10 V, R
L
= 2 k, C
L
= 100 pF [V
OUT
connected to R
FB
AD7837]. All specifications T
MIN
to T
MAX
unless otherwise noted.)
Parameter A Version B Version S Version Units Test Conditions/Comments
STATIC PERFORMANCE
Resolution 12 12 12 Bits
Relative Accuracy
2
±1 ±1/2 ±1 LSB max
Differential Nonlinearity
2
±1 ±1 ±1 LSB max Guaranteed Monotonic
Zero Code Offset Error
2
@ +25°C ±2 ±2 ±2 mV max DAC Latch Loaded with All 0s
T
MIN
to T
MAX
±4 ±3 ±4 mV max Temperature Coefficient = ±5 µV/°C typ
Gain Error
2
@ +25°C ±4 ±2 ±4 LSB max DAC Latch Loaded with All 1s
T
MIN
to T
MAX
±5 ±3 ±5 LSB max Temperature Coefficient = ±2 ppm of
FSR/°C typ
REFERENCE INPUTS
V
REF
Input Resistance 8/13 8/13 8/13 k min/max Typical Input Resistance = 10 k
V
REFA
, V
REFB
Resistance Matching ±2 ±2 ±2 % max Typically ±0.25%
DIGITAL INPUTS
Input High Voltage, V
INH
2.4 2.4 2.4 V min
Input Low Voltage, V
INL
0.8 0.8 0.8 V max
Input Current ±1 ±1 ±1 µA max Digital Inputs at 0 V and V
DD
Input Capacitance
3
8 8 8 pF max
ANALOG OUTPUTS
DC Output Impedance 0.2 0.2 0.2 typ
Short Circuit Current 11 11 11 mA typ V
OUT
Connected to AGND
POWER REQUIREMENTS
4
V
DD
Range 14.25/15.75 14.25/15.75 14.25/15.75 V min/max
V
SS
Range –14.25/–15.75 –14.25/–15.75 –14.25/–15.75 V min/max
Power Supply Rejection
Gain/V
DD
±0.01 ±0.01 ±0.01 % per % max V
DD
= 15 V ± 5%, V
REF
= –10 V
Gain/V
SS
±0.01 ±0.01 ±0.01 % per % max V
SS
= –15 V ± 5%, V
REF
= +10 V
I
DD
8 8 8 mA max Outputs Unloaded. Inputs at Thresholds.
Typically 5 mA
I
SS
6 6 6 mA max Outputs Unloaded. Inputs at Thresholds.
Typically 3 mA
AC CHARACTERISTICS
2, 3
Voltage Output Settling Time 3 3 3 µs typ Settling Time to Within ±1/2 LSB of Final
555µs max Value. DAC Latch Alternately Loaded
with All 0s and All 1s
Slew Rate 11 11 11 V/µs typ
Digital-to-Analog Glitch Impulse 10 10 10 nV secs typ 1 LSB Change Around Major Carry
Channel-to-Channel Isolation
V
REFA
to V
OUTB
–95 –95 –95 dB typ V
REFA
= 20 V p-p, 10 kHz Sine Wave.
DAC Latches Loaded with All 0s
V
REFB
to V
OUTA
–95 –95 –95 dB typ V
REFB
= 20 V p-p, 10 kHz Sine Wave.
DAC Latches Loaded with All 0s
Multiplying Feedthrough Error –90 –90 –90 dB typ V
REF
= 20 V p-p, 10 kHz Sine Wave.
DAC Latch Loaded with All 0s
Unity Gain Small Signal BW 750 750 750 kHz typ V
REF
= 100 mV p-p Sine Wave. DAC
Latch Loaded with All 1s
Full Power BW 175 175 175 kHz typ V
REF
= 20 V p-p Sine Wave. DAC
Latch Loaded with All 1s
Total Harmonic Distortion –88 –88 –88 dB typ V
REF
= 6 V rms, 1 kHz. DAC Latch
Loaded with All 1s
Digital Crosstalk 1 1 1 nV secs typ Code Transition from All 0s to All 1s and
Vice Versa
Output Noise Voltage @ +25°C See Typical Performance Graphs
(0.1 Hz to 10 Hz) 2 2 2 µV rms typ Amplifier Noise and Johnson Noise of R
FB
Digital Feedthrough 1 1 1 nV secs typ
NOTES
1
Temperature ranges are as follows: A, B Versions, –40°C to +85°C; S Version, –55°C to +125°C.
2
See Terminology.
3
Guaranteed by design and characterization, not production tested.
4
The Devices are functional with V
DD
/V
SS
= ± 12 V (See typical performance graphs.).
Specifications subject to change without notice.
AD7837/AD7847
REV. C
–3–
TIMING CHARACTERISTICS
1, 2, 3
Limit at T
MIN
, T
MAX
Parameter (All Versions) Unit Conditions/Comments
t
1
0 ns min CS to WR Setup Time
t
2
0 ns min CS to WR Hold Time
t
3
30 ns min WR Pulsewidth
t
4
80 ns min Data Valid to WR Setup Time
t
5
0 ns min Data Valid to WR Hold Time
t
6
4
0 ns min Address to WR Setup Time
t
7
4
0 ns min Address to WR Hold Time
t
8
4
50 ns min LDAC Pulsewidth
NOTES
1
All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figures 3 and 5.
3
Guaranteed by design and characterization, not production tested.
4
AD7837 only.
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25°C unless otherwise noted)
V
DD
to DGND, AGNDA, AGNDB . . . . . . . –0.3 V to +17 V
V
SS
1
to DGND, AGNDA, AGNDB . . . . . . . +0.3 V to –17 V
V
REFA
, V
REFB
to AGNDA, AGNDB
. . . . . . . . . . . . . . . . . . . . . . . . . . V
SS
– 0.3 V to V
DD
+ 0.3 V
AGNDA, AGNDB to DGND . . . . . . . –0.3 V to V
DD
+ 0.3 V
V
OUTA
2
, V
OUTB
2
to AGNDA, AGNDB
. . . . . . . . . . . . . . . . . . . . . . . . . . V
SS
– 0.3 V to V
DD
+ 0.3 V
R
FBA
3
, R
FBB
3
to AGNDA, AGNDB
. . . . . . . . . . . . . . . . . . . . . . . . . . V
SS
– 0.3 V to V
DD
+ 0.3 V
Digital Inputs to DGND . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Commercial/Industrial (A, B Versions) . . . –40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 300°C
Power Dissipation (Any Package) to +75°C . . . . . . 1000 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C
NOTES
1
If V
SS
is open circuited with V
DD
and either AGND applied, the V
SS
pin will float
positive, exceeding the Absolute Maximum Ratings. If this possibility exists, a
Schottky diode connected between V
SS
and AGND (cathode to AGND) ensures
the Maximum Ratings will be observed.
2
The outputs may be shorted to voltages in this range provided the power dissipation
of the package is not exceeded.
3
AD7837 only.
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability. Only one Absolute
Maximum Rating may be applied at any one time.
ORDERING GUIDE
Temperature Relative Package
Model
1
Range Accuracy Option
2
AD7837AN –40°C to +85°C ±1 LSB N-24
AD7837BN –40°C to +85°C ±1/2 LSB N-24
AD7837AR –40°C to +85°C ±1 LSB R-24
AD7837BR –40°C to +85°C ±1/2 LSB R-24
AD7837AQ –40°C to +85°C ±1 LSB Q-24
AD7837BQ –40°C to +85°C ±1/2 LSB Q-24
AD7837SQ –55°C to +125°C ±1 LSB Q-24
AD7847AN –40°C to +85°C ±1 LSB N-24
AD7847BN –40°C to +85°C ±1/2 LSB N-24
AD7847AR –40°C to +85°C ±1 LSB R-24
AD7847BR –40°C to +85°C ±1/2 LSB R-24
AD7847AQ –40°C to +85°C ±1 LSB Q-24
AD7847BQ –40°C to +85°C ±1/2 LSB Q-24
AD7847SQ –55°C to +125°C ±1 LSB Q-24
NOTES
1
To order MIL-STD-883, Class B processed parts, add /883B to part number.
2
N = Plastic DIP; Q = Cerdip; R = SOIC.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
(V
DD
= +15 V 5%, V
SS
= –15 V 5%, AGNDA = AGNDB = DGND = O V)
WARNING!
ESD SENSITIVE DEVICE
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