4-282
Functional Diagram
Gated Inputs
During normal system operation of a latch, signals on the
bus at the device inputs will become high impedance or
make transitions unrelated to the operation of the latch.
These unrelated input transitions switch the input circuitry
and typically cause an increase in power dissipation in
CMOS devices by creating a low resistance path between
V
CC
and GND when the signal is at or near the input switch-
ing threshold. Additionally, if the driving signal becomes high
impedance (``float'' condition), it could create an indetermi-
nate logic state at the inputs and cause a disruption in
device operation.
The Intersil 82C8X series of bus drivers eliminates these
conditions by turning off data inputs when data is latched
(STB = logic zero for the 82C82/83H) and when the device is
disabled (
OE = logic one for the 82C86H/87H). These gated
inputs disconnect the input circuitry from the V
CC
and
ground power supply pins by turning off the upper P-channel
and lower N-channel (See Figures 1 and 2). No current flow
from V
CC
to GND occurs during input transitions and invalid
logic states from floating inputs are not transmitted. The next
stage is held to a valid logic level internal to the device.
D.C. input voltage levels can also cause an increase in ICC if
these input levels approach the minimum V
IH
or maximum
V
IL
conditions. This is due to the operation of the input cir-
cuitry in its linear operating region (partially conducting
state). The 82C8X series gated inputs mean that this condi-
tion will occur only during the time the device is in the trans-
parent mode (STB = logic one). ICC remains below the
maximum ICC standby specification of 10µA during the time
inputs are disabled, thereby greatly reducing the average
power dissipation of the 82C8X series devices.
Decoupling Capacitors
The transient current required to charge and discharge the
300pF load capacitance specified in the 82C83H data sheet
is determined by
I = C
L
(dv/dt)
Assuming that all outputs change state at the same time and
that dv/dt is constant;
where t
R
= 20ns, V
CC
= 5.0V, C
L
= 300pF on each eight out-
puts.
I = (8 x 300 x 10
-12
) x (5.0V x 0.8)/(20 x 10
-9
) = 480mA
This current spike may cause a large negative voltage spike on
V
CC
which could cause improper operation of the device. To fil-
ter out this noise, it is recommended that a 0.1µF ceramic disc
capacitor be placed between V
CC
and GND at each device,
with placement being as near to the device as possible.
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
STB
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
OE
DQ
CLK
P
P
N
N
N
P
V
CC
V
CC
INTERNAL
DATA
STB
DATA IN
FIGURE 1. 82C82/83H
N
N
P
P
P
N
V
CC
V
CC
DATA
INTERNAL
OE
DATA IN
FIGURE 2. 82C86H/87H GATED INPUTS
IC
L
V
CC
80 percent×()
t
R
t
F
⁄
--------------------------------------------------------
=
(EQ. 1)
P
P
N
N
N
P
V
CC
V
CC
INTERNAL
DATA
STB
DATA IN
ADDRESS ADDRESS
ALE
MULTI-
ICC
PLEXED
BUS
FIGURE 3. SYSTEM EFFECTS OF GATED INPUTS
82C83H
