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74ALVC162835DGG

Part # 74ALVC162835DGG
Description IC UNIV BUS DVR 18BIT 56TSSOP
Category IC
Availability In Stock
Qty 69
Qty Price
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44 - 57 $5.61489
58 + $5.00457
Manufacturer Available Qty
Philips Semiconductor
Date Code: 9941
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Philips Semiconductor
Date Code: 9944
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

www.ti.com
FEATURES
DESCRIPTION/ORDERING INFORMATION
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NC
NC
Y1
GND
Y2
Y3
V
CC
Y4
Y5
Y6
GND
Y7
Y8
Y9
Y10
Y11
Y12
GND
Y13
Y14
Y15
V
CC
Y16
Y17
GND
Y18
OE
LE
GND
NC
A1
GND
A2
A3
V
CC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
V
CC
A16
A17
GND
A18
CLK
GND
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
NC − No internal connection
SN74ALVC162835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES126H FEBRUARY 1998 REVISED SEPTEMBER 2004
Member of the Texas Instruments Widebus™
Family
Operates From 1.65 V to 3.6 V
Max t
pd
of 2 ns at 3.3 V
± 12-mA Output Drive at 3.3 V
Ideal for Use in PC100 Register DIMM,
Revision 1.1
Output Port Has Equivalent 26- Series
Resistors, So No External Resistors Are
Required
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
This 18-bit universal bus driver is designed for 1.65-V
to 3.6-V V
CC
operation.
Data flow from A to Y is controlled by the
output-enable ( OE) input. The device operates in the
transparent mode when the latch-enable (LE) input is
high. When LE is low, the A data is latched if the
clock (CLK) input is held at a high or low logic level. If
LE is low, the A data is stored in the latch/flip-flop on
the low-to-high transition of CLK. When OE is high,
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up
or power down, OE should be tied to V
CC
through a
pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the
driver.
The output port includes equivalent 26- series
resistors to reduce overshoot and undershoot.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
Tube SN74ALVC162835DL
SSOP - DL ALVC162835
Tape and reel SN74ALVC162835DLR
-40 ° C to 85 ° C
TSSOP - DGG Tape and reel SN74ALVC162835DGGR ALVC162835
TVSOP - DGV Tape and reel SN74ALVC162835DGVR VC2835
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1998–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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OE
CLK
Y1
1D
C1
CLK
To 17 Other Channels
LE
A1
27
30
28
54
3
ABSOLUTE MAXIMUM RATINGS
(1)
SN74ALVC162835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES126H FEBRUARY 1998 REVISED SEPTEMBER 2004
FUNCTION TABLE
INPUTS
OUTPUT
Y
OE LE CLK A
H X X X Z
L H X L L
L H X H H
L L L L
L L H H
L L L or H X Y
0
(1)
(1) Output level before the indicated steady-state input conditions were
established
LOGIC DIAGRAM (POSITIVE LOGIC)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range -0.5 4.6 V
V
I
Input voltage range
(2)
-0.5 4.6 V
V
O
Output voltage range
(2) (3)
-0.5 V
CC
+ 0.5 V
I
IK
Input clamp current V
I
< 0 -50 mA
I
OK
Output clamp current V
O
< 0 -50 mA
I
O
Continuous output current ± 50 mA
Continuous current through each V
CC
or GND ± 100 mA
DGG package 64
θ
JA
Package thermal impedance
(4)
DGV package 48 ° C/W
DL package 56
T
stg
Storage temperature range -65 150 ° C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) This value is limited to 4.6 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
2
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RECOMMENDED OPERATING CONDITIONS
(1)
SN74ALVC162835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES126H FEBRUARY 1998 REVISED SEPTEMBER 2004
MIN MAX UNIT
V
CC
Supply voltage 1.65 3.6 V
V
CC
= 1.65 V to 1.95 V 0.65 × V
CC
V
IH
High-level input voltage V
CC
= 2.3 V to 2.7 V 1.7 V
V
CC
= 2.7 V to 3.6 V 2
V
CC
= 1.65 V to 1.95 V 0.35 × V
CC
V
IL
Low-level input voltage V
CC
= 2.3 V to 2.7 V 0.7 V
V
CC
= 2.7 V to 3.6 V 0.8
V
I
Input voltage 0 3.6 V
V
O
Output voltage 0 V
CC
V
V
CC
= 1.65 V -2
V
CC
= 2.3 V -6
I
OH
High-level output current mA
V
CC
= 2.7 V -8
V
CC
= 3 V -12
V
CC
= 1.65 V 2
V
CC
= 2.3 V 6
I
OL
Low-level output current mA
V
CC
= 2.7 V 8
V
CC
= 3 V 12
t/ v Input transition rise or fall rate 10 ns/V
T
A
Operating free-air temperature -40 85 ° C
(1) All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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