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74ALVC162244T

Part # 74ALVC162244T
Description BFFR/LINE DRVR 16CH NON-INV 3-ST CMOS 48TSSOP W - Rail/Tub
Category IC
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Fairchild Semiconductor
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

© 2001 Fairchild Semiconductor Corporation DS500696 www.fairchildsemi.com
November 2001
Revised November 2001
74ALVC162244 Low Voltage 16-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs and 26
Series
Resistor in Outputs
74ALVC162244
Low Voltage 16-Bit Buffer/Line Driver
with 3.6V Tolerant Inputs and Outputs
and 26
Series Resistor in Outputs
General Description
The ALVC162244 contains sixteen non-inverting buffers
with 3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver. The device is nibble (4-bit) controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The 74ALVC162244 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O capability up to 3.6V. The
74ALVC162244 is also designed with 26
series resistors
in the outputs. This design reduces line noise in applica-
tions such as memory address drivers, clock drivers, and
bus transceivers/transmitters.
The 74ALVC162244 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
1.65V to 3.6V V
CC
supply operation
3.6V tolerant inputs and outputs
26
series resistors in outputs
t
PD
3.8 ns max for 3.0V to 3.6V V
CC
4.3 ns max for 2.3V to 2.7V V
CC
7.6 ns max for 1.65V to 1.95V V
CC
Power-off high impedance inputs and outputs
Supports live insertion and withdrawal
Uses patented noise/EMI reduction circuitry
Latchup conforms to JEDEC JED78
ESD performance:
Human body model
> 2000V
Machine model
> 200V
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Note 1: To ensure the high-impedance state during power up or power
down, OE
should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Note 2: BGA package available in Tape and Reel only.
Note 3: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Order Number Package Number Package Description
74ALVC162244GX
(Note 2)
BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]
74ALVC162244T
(Note 3)
MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
www.fairchildsemi.com 2
74ALVC162244
Logic Symbol
Connection Diagrams
Pin Assignment for TSSOP
Pin Assignment for FBGA
(Top Thru View)
Pin Descriptions
FBGA Pin Assignments
Truth Tables
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance
Pin Names Description
OE
n
Output Enable Input (Active LOW)
I
0
I
15
Inputs
O
0
O
15
Outputs
NC No Connect
123456
A O
0
NC OE
1
OE
2
NC I
0
B O
2
O
1
NC NC I
1
I
2
C O
4
O
3
V
CC
V
CC
I
3
I
4
D O
6
O
5
GND GND I
5
I
6
E O
8
O
7
GND GND I
7
I
8
F O
10
O
9
GND GND I
9
I
10
G O
12
O
11
V
CC
V
CC
I
11
I
12
H O
14
O
13
NC NC I
13
I
14
J O
15
NC OE
4
OE
3
NC I
15
Inputs Outputs
OE
1
I
0
–I
3
O
0
–O
3
LL L
LH H
HX Z
Inputs Outputs
OE
2
I
4
–I
7
O
4
–O
7
LL L
LH H
HX Z
Inputs Outputs
OE
3
I
8
–I
11
O
8
–O
11
LL L
LH H
HX Z
Inputs Outputs
OE
4
I
12
–I
15
O
12
–O
15
LL L
LH H
HX Z
3 www.fairchildsemi.com
74ALVC162244
Functional Description
The 74ALVC162244 contains sixteen non-inverting buffers
with 3-STATE outputs. The device is nibble (4 bits) con-
trolled with each nibble functioning identically, but indepen-
dent of each other. The control pins may be shorted
together to obtain full 16-bit operation.The 3-STATE out-
puts are controlled by an Output Enable (OE
n
) input. When
OE
n
is LOW, the outputs are in the 2-state mode. When
OE
n
is HIGH, the standard outputs are in the high imped-
ance mode but this does not interfere with entering new
data into the inputs.
Logic Diagram
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