SA 10136F

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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Semiconductor Components Industries, LLC, 2002
January, 2002 – Rev. 7
1 Publication Order Number:
MC10136/D
MC10136
Universal Hexadecimal
Counter
The MC10136 is a high speed synchronous counter that can count
up, count down, preset, or stop count at frequencies exceeding 100
MHz. The flexibility of this device allows the designer to use one basic
counter for most applications, and the synchronous count feature
makes the MC10136 suitable for either computers or instrumentation.
Three control lines (S1, S2, and Carry In
) determine the operation
mode of the counter. Lines S1 and S2 determine one of four
operations; preset (program), increment (count up), decrement (count
down), or hold (stop count). Note that in the preset mode a clock pulse
is necessary to load the counter, and the information present on the
data inputs (D0, D1, D2, and D3) will be entered into the counter.
Carry Out
goes low on the terminal count, or when the counter is being
preset.
This device is not designed for use with gated clocks. Control is via
S1 and S2.
P
D
= 625 mW typ/pkg (No Load)
f
count
= 150 MHz typ
t
pd
= 3.3 ns typ (C-Q)
7.0 ns typ (C-C
out
)
5.0 ns typ (C
in
-C
out
)
DIP PIN ASSIGNMENT
V
CC1
Q2
Q3
C
out
D3
D2
S2
V
EE
V
CC2
Q1
Q0
CLOCK
D0
D1
C
in
S1
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
FUNCTION TABLE
C
in
S1 S2 Operating Mode
X L L Preset (Program)
L L H Increment (Count Up)
H L H Hold Count
L H L Decrement (Count Down)
H H L Hold Count
X H H Hold (Stop Count)
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Device Package Shipping
ORDERING INFORMATION
MC10136L CDIP–16 25 Units / Rail
MC10136P PDIP–16 25 Units / Rail
MC10136FN PLCC–20 46 Units / Rail
MARKING
DIAGRAMS
1
16
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
CDIP–16
L SUFFIX
CASE 620
MC10136L
AWLYYWW
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
10136
AWLYYWW
1
1
16
MC10136P
AWLYYWW
MC10136
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2
Q2T
T
T
T
T
T T
Q3
T
Q3
Q1
Q1T
T
C
T
C
T
C
Q0
LOGIC DIAGRAM
NOTE: Flip-flops will toggle when all T inputs are low.
S1 9
S2 7
Carry In
10
Clock
13
12D0 14Q0 11D1 15Q1 6D2 2Q2 5D3 3Q3 4 Carry Out
T
C
Q0
T
Q2
V
CC1
= PIN 1
V
CC2
= PIN 16
V
EE
= PIN 8
SEQUENTIAL TRUTH TABLE*
INPUTS OUTPUTS
S1 S2 D0 D1 D2 D3
Carry
In
Clock
**
Q0 Q1 Q2 Q3
Carry
Out
L L L L H H X H L L H H L
L H X X X X L H H L H H H
L H X X X X L H L H H H H
L H X X X X L H H H H H L
L H X X X X H L H H H H H
L H X X X X H H H H H H H
H H X X X X X H H H H H H
L L H H L L X H H H L L L
H L X X X X L H L H L L H
H L X X X X L H H L L L H
H L X X X X L H L L L L L
H L X X X X L H H H H H H
* Truth table shows logic states assuming inputs vary in sequence shown from top to bottom.
** A clock H is defined as a clock input transition from a low to a high logic level.
MC10136
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3
ELECTRICAL CHARACTERISTICS
Test Limits
Pin
Under
–30°C +25°C +85°C
Characteristic Symbol
U
n
d
er
Test
Min Max Min Typ Max Min Max
Unit
Power Supply Drain Current I
E
8 138 100 125 138 mAdc
Input Current I
inH
5,6,11,12
7
9,10
13
350
425
390
460
220
265
245
290
220
265
245
290
µAdc
I
inL
All 0.5 0.5 0.3 µAdc
Output Voltage Logic 1 V
OH
14 (2.) –1.060 –0.890 –0.960 –0.810 –0.890 –0.700 Vdc
Output Voltage Logic 0 V
OL
14 (2.) –1.890 –1.675 –1.850 –1.650 –1.825 –1.615 Vdc
Threshold Voltage Logic 1 V
OHA
14 (2.) –1.080 –0.980 –0.910 Vdc
Threshold Voltage Logic 0 V
OLA
14 (2.) –1.655 –1.630 –1.595 Vdc
Switching Times (50 Load) ns
Propagation DelayClock Input t
13+14+
t
13+14–
t
13+4+
t
13+4–
14
14
4
4
0.8
0.8
2.0
2.0
4.8
4.8
10.9
10.9
1.0
1.0
2.5
2.5
3.3
3.3
7.0
7.0
4.5
4.5
10.5
10.5
1.4
1.4
2.4
2.4
5.0
5.0
11.5
11.5
Carry In to Carry Out t
10–4–
t
10+4+
4 (3.)
4
1.6
1.6
7.4
7.4
1.6
1.6
5.0
5.0
6.9
6.9
1.9
1.9
7.5
7.5
Setup Time Data Inputs t
12+13+
t
12–13+
14
14
3.5
3.5
3.5
3.5
3.5
3.5
Select Inputs t
9+13+
t
7+13+
14
14
6.0
6.0
6.0
6.0
6.0
6.0
Carry In Input t
10–13+
t
10+13+
14
14
2.5
1.5
2.5
1.5
3.0
1.5
Hold Time Data Inputs t
13+12+
t
13+12–
14
14
0
0
0
0
0
0
Select Inputs t
13+9+
t
13+7+
14
14
–1.0
–1.0
–1.0
–1.0
–1.0
–1.0
Carry In Input t
13+10–
t
13+10+
14
14
0
0
0
0
0
0
Counting Frequency f
countup
f
countdown
14
14
125
125
125
125
150
150
125
125
MHz
Rise Time (20 to 80%) t
4+
t
14+
4
14
0.9
0.9
3.3
3.3
1.1
1.1
2.0
2.0
3.3
3.3
1.1
1.1
3.5
3.5
ns
Fall Time (20 to 80%) t
4–
t
14–
4
14
0.9
0.9
3.3
3.3
1.1
1.1
2.0
2.0
3.3
3.3
1.1
1.1
3.5
3.5
1. Individually test each input; apply V
ILmin
to pin under test.
2. Measure output after clock pulse
V
IH
V
IL
appears at clock input (Pin 13).
3. Before test set all Q outputs to a logic high.
4. To preserve reliable performance, the MC10136 (plastic packaged device only) is to be operated in ambient temperatures above 70°C only
when 500lfpm blown air or equivalent heat sinking is provided.
123NEXT

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