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UT54ACS164245S
RadHard Schmitt CMOS 16-bit Bidirectional MultiPurpose Transceiver
Datasheet
April , 2002
FEATURES
• Voltage translation
- 5V bus to 3.3V bus
- 3.3V bus to 5V bus
• Cold sparing
- 1MΩ minimum input impedance power-off
• 0.6µm Commercial RadHard
TM
CMOS
- Total dose: 100K rad(Si)
- Single Event Latchup immune
• High speed, low power consumption
• Schmitt trigger inputs to filter noisy signals
• Available QML Q or V processes
• Standard Microcircuit Drawing 5962-98580
• Package:
- 48-lead flatpack, 25 mil pitch (.390 x .640)
DESCRIPTION
The 16-bit wide UT54ACS164245S MultiPurpose transceiver
is built using UTMC’s Commercial RadHard
TM
epitaxial
CMOS technology and is ideal for space applications. This high
speed, low power UT54ACS164245S transceiver is designed to
perform multiple functions including: asynchronous two-way
communication, signal buffering, voltage translation, and cold
sparing. With V
DD
equal to zero volts, the UT54ACS164245S
outputs and inputs present a minimum impedance of 1MΩ mak-
ing it ideal for "cold spare" applications. Balanced outputs and
low "on" output impedance make the UT54ACS164245S well
suited for driving high capacitance loads and low impedance
backplanes. The UT54ACS164245S enables system designers
to interface 3.3 volt CMOS compatible components with 5 volt
CMOS components. For voltage translation, the A port inter-
faces with the 3.3 volt bus; the B port interfaces with the 5 volt
bus. The direction control (DIRx) controls the direction of data
flow. The output enable (OEx) overrides the direction control
and disables both ports. These signals can be driven from either
port A or B. The direction and output enable controls operate
these devices as either two independent 8-bit transceivers or one
16-bit transceiver.
LOGIC SYMBOL
PIN DESCRIPTION
FUNCTION TABLE
Pin Names Description
OEx Output Enable Input (Active Low)
DIRx Direction Control Inputs
xAx Side A Inputs or 3-State Outputs (3.3V Port)
xBx Side B Inputs or 3-State Outputs (5V Port)
ENABLE
OEx
DIRECTION
DIRx OPERATION
L L B Data To A Bus
L H A Data To B Bus
H X Isolation
(48)OE1
G2
(47)
1A1
(46)
1A2
(44)
(2)
1B1
(5)
(3)
1B2
1A3
(43)
1A4
(41)
1A5
(40)
1A6
1B3
(9)
1B6
(8)
1B5
(6)
1B4
(38)
1A7
(37)
1A8
(12)
1B8
(11)
1B7
(1)
DIR1 1EN1 (BA)
1EN2 (AB)
11
12
(25)OE2
G1
(24)
DIR2
21
22
(36)
2A1
2B1
(13)
(35)
2A2
(33)
2A3
(32)
2A4
(30)
2A5
(29)
2A6
(27)
2A7
(26)
2A8
(16)
2B2
2B3
(20)
2B6
(19)
2B5
(17)
2B4
(23)
2B8
(22)
2B7
(14)
2EN1 (BA)
2EN2 (AB)
