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5962R9858002VXC

Part # 5962R9858002VXC
Description RadHard Schmitt CMOS 16-Bit3.3V 48Pin Quad Flat Pack
Category IC
Availability In Stock
Qty 3
Qty Price
1 - 2 $359.37341
3 + $272.25258
Manufacturer Available Qty
UTMC
Date Code: 0324
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

4
RADIATION HARDNESS SPECIFICATIONS
1
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Not tested, inherent of CMOS technology.
ABSOLUTE MAXIMUM RATINGS
1
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability and performance.
DUAL SUPPLY OPERATING CONDITIONS
PARAMETER LIMIT UNITS
Total Dose 1.0E5 rad(Si)
SEL Latchup >120
MeV-cm
2
/mg
Neutron Fluence
2
1.0E14
n/cm
2
SYMBOL PARAMETER LIMIT (Mil only) UNITS
V
I/O
Voltage any pin -.3 to V
DD1
+.3 V
V
DD1
Supply voltage -0.3 to 6.0 V
V
DD2
Supply voltage -0.3 to 6.0 V
T
STG
Storage Temperature range -65 to +150 °C
T
J
Maximum junction temperature +175 °C
Θ
JC
Thermal resistance junction to case 20 °C/W
I
I
DC input current ±10 mA
P
D
Maximum power dissipation 1 W
SYMBOL PARAMETER LIMIT UNITS
V
DD1
Supply voltage 3.0 to 3.6 or 4.5 to 5.5 V
V
DD2
Supply voltage 3.0 to 3.6 or 4.5 to 5.5 V
V
IN
Input voltage any pin 0 to V
DD1
V
T
C
Temperature range -55 to + 125 °C
5
DC ELECTRICAL CHARACTERISTICS
1
( -55°C < T
C
< +125°C) (T
C
= -55°°C to +125°°C for "C" screening and -40°°C to +125°°C for "W" screening)
SYMBOL PARAMETER CONDITION MIN MAX UNIT
V
T
+
Schmitt Trigger, positive going
threshold
2
V
DD
from 3.00 to 5.5 .7V
DD
V
V
T
-
Schmitt Trigger, negative going threshold
2
V
DD
from 3.00 to 5.5 .3V
DD
V
V
H1 Schmitt Trigger range of hysteresis
10
V
DD
from 4.5
to 5.5
0.6 V
V
H2 Schmitt Trigger range of hysteresis
10
V
DD
from 3.00 to 3.6 0.4 V
I
IN Input leakage current
10
V
DD
from 3.6 to 5.5
V
IN
= V
DD
or V
SS
-1 3 µA
I
OZ Three-state output leakage current
10
V
DD
from 3.6 to 5.5
V
IN
= V
DD
or V
SS
-1 3 µA
I
CS Cold sparing leakage current
3
V
IN
= 5.5
V
DD
= V
SS
-1 5 µA
I
OS1 Short-circuit output current
6, 11
V
O
= V
DD
or V
SS
V
DD
from 4.5 to 5.5
-200 200 mA
I
OS2 Short-circuit output current
6, 11
V
O
= V
DD
or V
SS
V
DD
from 3.00 to 3.6
-100 100 mA
V
OL1
Low-level output voltage
4, 10
I
OL
= 8mA
I
OL
= 100µA
V
DD
= 4.5
0.4
0.2
V
V
OL2
Low-level output voltage
4, 10
I
OL
= 8mA
I
OL
= 100µA
V
DD
= 3.00
0.5
0.2
V
V
OH1 High-level output voltage
4, 10
I
OH
= -8mA
I
OH
= -100µA
V
DD
= 4.5
V
DD
- 0.7
V
DD
- 0.2
V
V
OH2 High-level output voltage
4, 10
I
OH
= -8mA
I
OH
= -100µA
V
DD
= 3.00
V
DD
- 0.9
V
DD
- 0.2
V
6
Notes:
1. All specifications valid for radiation dose ≤ 1E5 rad(Si) per MIL-STD-883, Method 1019.
2. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V
IH
= V
IH
(min) + 20%, - 0%; V
IL
= V
IL
(max) + 0%,
- 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within th e above specified range, but
are guaranteed to V
IH
(min) and V
IL
(max).
3. All combinations of OEx and DIRx
4. Per MIL-PRF-38535, for current density ≤ 5.0E5 amps/cm
2
, the maximum product of load capacitance (per output buffer) times frequency should not exceed
3,765 pF-MHz.
5. Guaranteed by characterization.
6. Not more than one output may be shorted at a time for maximum duration of one second.
7. Power does not include power contribution of any CMOS output sink current.
8. Power dissipation specified per switching output.
9.Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and V
SS
at frequency of 1MHz and a signal amplitude of 50mV rms maximum.
10.Guaranteed; tested on a sample of pins per device.
11. Supplied as a design limit, but not guaranteed or tested.
.
P
total1 Power dissipation
5,7, 8
C
L
= 50pF
V
DD
from 4.5 to 5.5
2.0 mW/
MHz
P
total2
Power dissipation
5, 7, 8
C
L
= 50pF
V
DD
from 3.00 to 3.6
1.5 mW/
MHz
I
DD
Standby Supply Current V
DD1
or V
DD2
Pre-Rad 25
o
C
Pre-Rad -55
o
C to +125
o
C
Post-Rad 25
o
C
V
IN
= V
DD
or V
SS
V
DD
= 5.5
OE=V
DD
OE=V
DD
OE=V
DD
10
100
500
µA
µA
µA
C
IN Input capacitance
9
ƒ = 1MHz @ 0V
V
DD
from 3.00 to 5.5
15 pF
C
OUT Output capacitance
9
ƒ = 1MHz @ 0V
V
DD
from 3.00 to 5.5
15 pF
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