OFC 12B53-2

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Technical Document


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XC6101_07_XC6111_17 ETR0207_009
Preliminary
CMOS Voltage Detector
Manual Reset Input
Watchdog Functions
Built-in Delay Circuit
Detect Voltage Range: 1.6~5.0V, ± 2%
Reset Function is Selectable
VDFL (Low When Detected)
VDFH (High When Detected)
GENERAL DESCRIPTION
The XC6101~XC6107, XC6111~XC6117 series are
groups of high-precision, low current consumption voltage
detectors with manual reset input function and watchdog
functions incorporating CMOS process technology. The
series consist of a reference voltage source, delay circuit,
comparator, and output driver.
With the built-in delay circuit, the XC6101 ~ XC6107,
XC6111 ~ XC6117 series’ ICs do not require any external
components to output signals with release delay time.
Moreover, with the manual reset function, reset can be
asserted at any time. The ICs produce two types of
output; V
DFL (low when detected) and VDFH (high when
detected).
With the XC6101 ~ XC6105, XC6111 ~ XC6115 series’
ICs, the WD pin can be left open if the watchdog function
is not used.
Whenever the watchdog pin is opened, the internal
counter clears before the watchdog timeout occurs.
Since the manual reset pin is internally pulled up to the V
IN
pin voltage level, the ICs can be used with the manual
reset pin left unconnected if the pin is unused.
The detect voltages are internally fixed 1.6V ~ 5.0V in
increments of 100mV, using laser trimming technology.
Six watchdog timeout period settings are available in a
range from 6.25msec to 1.6sec.
Seven release delay time 1 are available in a range from
3.13msec to 1.6sec.
A
PPLICATIONS
Microprocessor reset circuits
Memory battery backup circuits
System power-on reset circuits
Power failure detection
TYPICAL APPLICATION CIRCUIT
* Not necessary with CMOS output products.
FEATURES
Detect Voltage Range : 1.6V ~ 5.0V, +2%
(100mV increments)
Hysteresis Range : VDF x 5%, TYP.
(XC6101~XC6107)
VDF x 0.1%, TYP.
(XC6111~XC6117)
Operating Voltage Range : 1.0V ~ 6.0V
Detect Voltage Temperature
Characteristics
: +100ppm/
O
C (TYP.)
Output Configuration : N-channel open drain,
CMOS
Watchdog Pin : Watchdog input
If watchdog input maintains
‘H’ or ‘L within the watchdog
timeout period, a reset signal
is output to the RESET
output pin
Manual Reset Pin : When driven ‘H’ to ‘L’ level
signal, the MRB pin voltage
asserts forced reset on the
output pin.
Release Delay Time : 1.6sec, 400msec, 200msec,
100msec, 50msec, 25msec,
3.13msec (TYP.) can be
selectable.
Watchdog Timeout Period : 1.6sec, 400msec, 200msec,
100msec, 50msec,
6.25msec (TYP.) can be
selectable.
TYPICAL PERFORMANCE
CHARACTERISTICS
Supply Current vs. Input Voltage
* ‘x’ represents both ‘0’ and ‘1’. (ex. XC61x1XC6101 and XC6111)
0
5
10
15
20
25
30
0123456
Input Voltage:
 
VIN (V)
Supply Current:
 
ISS (µA)
XC6 1 X1~ XC6 1X5 (2 . 7 V )
Ta=85
Ta= -40
Ta= 25
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XC6101~XC6107, XC6111~XC6117 Series
PIN NUMBER
XC6101, XC6102 XC6103 XC6104, XC6105 XC6106, XC6107
XC6111, XC6112 XC6113 XC6114, XC6115 XC6116, XC6117
SOT-25 USP-6C SOT-25 USP-6C SOT-25 USP-6C SOT-25 USP-6C
PIN NAME FUNCTION
1 4 - - 1 4 1 4
RESETB
Reset Output
(V
DFL: Low Level When Detected)
2 5 2 5 2 5 2 5
V
SS
Ground
3 2 3 2 - - 4 1 MRB Manual Reset
4 1 4 1 4 1 - - WD Watchdog
5 6 5 6 5 6 5 6 VIN Power Input
- - 1 4 3 2 3 2 RESET
Reset Output
(V
DFH: High Level When Detected)
PIN CONFIGURATION
SOT-25 (TOP VIEW)
MRB
V
IN
WD
5
RESETB
V
SS
4
123
MRB
WD
5
RESET
V
SS
4
123
V
IN
RESET
WD
5
RESETB
V
SS
4
123
V
IN
SOT-25 (TOP VIEW)
RESET
MRB
5
RESETB
V
SS
4
123
V
IN
SOT-25 (TOP VIEW)
PIN ASSIGNMENT
SOT-25
XC6101, XC6102 Series
XC6111, XC6112 Series
SOT-25 (TOP VIEW)
XC6103 & XC6113 Series
XC6104, XC6105 Series
XC6114, XC6115 Series
XC6106, XC6107 Series
XC6116, XC6117 Series
USP-6C
XC6101, XC6102 Series
XC6111, XC6112 Series
XC6103 & XC6113 Series
XC6104, XC6105 Series
XC6114, XC6115 Series
XC6106, XC6107 Series
XC6116, XC6117 Series
USP-6C (BOTTOM VIEW)
USP-6C (BOTTOM VIEW) USP-6C (BOTTOM VIEW)
USP-6C (BOTTOM VIEW)
* The dissipation pad for the USP-6C package should be
solder-plated in recommended mount pattern and metal
masking so as to enhance mounting strength and heat
release. If the pad needs to be connected to other pins, it
should be connected to the V
SS pin.
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XC6101 ~ XC6107, XC6111~ XC6117
Series
RESET OUTPUT
SERIES WATCHDOG
MANUAL
RESET
VDFL (RESETB) VDFH (RESET)
XC6101 XC6111 Available Available CMOS -
XC6102 XC6112 Available Available N-channel open drain -
XC6103 XC6113 Available Available - CMOS
XC6104 XC6114 Available Not Available CMOS CMOS
XC6105 XC6115 Available Not Available N-channel open drain CMOS
XC6106 XC6116 Not Available Available CMOS CMOS
XC6107 XC6117 Not Available Available N-channel open drain CMOS
DESIGNATOR DESCRIPTION SYMBOL DESCRIPTION
0 : VDF x 5% (TYP.) with hysteresis
Hysteresis Range
1 : V
DF x 0.1% (TYP.) without hysteresis
Functions and
Type of Reset Output
1 ~ 7
: Watchdog and manual functions, and reset
output type as per Selection Guide in the above
chart
A : 3.13msec (TYP.)
B : 25msec (TYP.)
C : 50msec (TYP.)
D : 100msec (TYP.)
E : 200msec (TYP.)
F : 400msec (TYP.)
Release Delay Time *
H : 1.6sec (TYP.)
0
: No WD timeout period for
XC6106, XC6107, XC6116, XC6117 Series
1 : 6.25msec (TYP.)
2 : 50msec (TYP.)
3 : 100msec (TYP.)
4 : 200msec (TYP.)
5 : 400msec (TYP.)
Watchdog Timeout Period
6 : 1.6sec (TYP.)
⑤⑥ Detect Voltage 16 ~ 50
: Detect voltage
ex.) 4.5V: ⑤⇒4, ⑥⇒5
M : SOT-25
Package
E : USP-6C
R : Embossed tape, standard feed
Device Orientation
L : Embossed tape, reverse feed
* Please set the release delay time shorter than or equal to the watchdog timeout period.
ex.) XC6101D427MR or XC6101D327MR
PRODUCT CLASSIFICATION
Selection Guide
Ordering Information
XC61①②③④⑤⑥⑦⑧
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