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MAX149AEAP

Part # MAX149AEAP
Description +2.7V TO +5.25V LOW-POWER 8-CHANNEL SERIAL 10-BIT ADCS - B
Category CONVERTER
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MAXIM
Date Code: 0104
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

MAX148/MAX149
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
10 ______________________________________________________________________________________
How to Start a Conversion
Start a conversion by clocking a control byte into DIN.
With CS low, each rising edge on SCLK clocks a bit from
DIN into the MAX148/MAX149’s internal shift register.
After CS falls, the first arriving logic “1” bit defines the
control byte’s MSB. Until this first “start” bit arrives, any
number of logic “0” bits can be clocked into DIN with no
effect. Table 1 shows the control-byte format.
The MAX148/MAX149 are compatible with SPI/
QSPI and MICROWIRE devices. For SPI, select the cor-
rect clock polarity and sampling edge in the SPI control
registers: set CPOL = 0 and CPHA = 0. MICROWIRE,
SPI, and QSPI all transmit a byte and receive a byte at
the same time. Using the
Typical Operating Circuit,
the
simplest software interface requires only three 8-bit
transfers to perform a conversion (one 8-bit transfer to
configure the ADC, and two more 8-bit transfers to clock
out the conversion result). See Figure 20 for MAX148/
MAX149 QSPI connections.
BIT NAME DESCRIPTION
7(MSB) START The first logic “1” bit after CS goes low defines the beginning of the control byte.
6 SEL2 These three bits select which of the eight channels are used for the conversion (Tables 2 and 3).
5 SEL1
4 SEL0
3 UNI/BIP 1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an
analog input signal from 0V to VREF can be converted; in bipolar mode, the signal can range
from -VREF/2 to +VREF/2.
2 SGL/DIF 1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-
ended mode, input signal voltages are referred to COM. In differential mode, the voltage
difference between two channels is measured (Tables 2 and 3).
1 PD1 Selects clock and power-down modes.
0(LSB) PD0 PD1 PD0 Mode
0 0 Full power-down
0 1 Fast power-down (MAX149 only)
1 0 Internal clock mode
1 1 External clock mode
Table 1. Control-Byte Format
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
(MSB) (LSB)
START SEL2 SEL1 SEL0 UNI/BIP
SGL/DIF PD1 PD0
SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM
0 0 0 +
1 0 0 +
0 0 1 +
1 0 1 +
0 1 0 +
1 1 0 +
0 1 1 +
1 1 1 +
Table 2. Channel Selection in Single-Ended Mode (SGL/
DDIIFF
= 1)
MAX148/MAX149
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
______________________________________________________________________________________ 11
Simple Software Interface
Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 2MHz.
1) Set up the control byte for external clock mode and
call it TB1. TB1 should be of the format: 1XXXXX11
binary, where the Xs denote the particular channel
and conversion mode selected.
2) Use a general-purpose I/O line on the CPU to pull
CS low.
3) Transmit TB1 and, simultaneously, receive a byte
and call it RB1. Ignore RB1.
4) Transmit a byte of all zeros ($00 hex) and, simulta-
neously, receive byte RB2.
5) Transmit a byte of all zeros ($00 hex) and, simulta-
neously, receive byte RB3.
6) Pull CS high.
Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion, padded
with one leading zero, two sub-LSB bits, and three trail-
ing zeros. The total conversion time is a function of the
serial-clock frequency and the amount of idle time
between 8-bit transfers. To avoid excessive T/H droop,
make sure the total conversion time does not exceed
120µs.
Digital Output
In unipolar input mode, the output is straight binary
(Figure 17). For bipolar input mode, the output is twos
complement (Figure 18). Data is clocked out at the
falling edge of SCLK in MSB-first format.
Clock Modes
The MAX148/MAX149 may use either an external
serial clock or the internal clock to perform the succes-
sive-approximation conversion. In both clock modes,
the external clock shifts data in and out of the
Figure 6. 24-Clock External Clock Mode Conversion Timing (MICROWIRE and SPI-Compatible, QSPI-Compatible with f
SCLK
2MHz)
SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
0 0 0 +
0 0 1 +
0 1 0 +
0 1 1 +
1 0 0 +
1 0 1 +
1 1 0 +
1 1 1 +
Table 3. Channel Selection in Differential Mode (SGL/
DDIIFF
= 0)
MAX148/MAX149
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
12 ______________________________________________________________________________________
MAX148/MAX149. The T/H acquires the input signal as
the last three bits of the control byte are clocked into
DIN. Bits PD1 and PD0 of the control byte program the
clock mode. Figures 7–10 show the timing characteris-
tics common to both modes.
External Clock
In external clock mode, the external clock not only shifts
data in and out, but it also drives the analog-to-digital
conversion steps. SSTRB pulses high for one clock
period after the last bit of the control byte. Succes-
sive-approximation bit decisions are made and appear
at DOUT on each of the next 12 SCLK falling edges
(Figure 6). SSTRB and DOUT go into a high-impedance
state when CS goes high; after the next CS falling edge,
SSTRB outputs a logic low. Figure 8 shows the SSTRB
timing in external clock mode.
The conversion must complete in some minimum time,
or droop on the sample-and-hold capacitors may
degrade conversion results. Use internal clock mode if
the serial-clock frequency is less than 100kHz, or if
serial-clock interruptions could cause the conversion
interval to exceed 120µs.
Internal Clock
In internal clock mode, the MAX148/MAX149 generate
their own conversion clocks internally. This frees the µP
Figure 8. External Clock Mode SSTRB Detailed Timing
Figure 7. Detailed Serial-Interface Timing
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