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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Semiconductor Components Industries, LLC, 2003
April, 2003 - Rev. 1
1 Publication Order Number:
ECLLQFP32EVB/D
ECLLQFP32EVB
Evaluation Board Manual
for High Frequency
LQFP32
INTRODUCTION
ON Semiconductor has developed an evaluation board for
the devices in 32-lead LQFP package. These evaluation
boards are offered as a convenience for the customers
interested in performing their own engineering assessment
on the general performance of the 32-lead LQFP device
samples. The board provides a high bandwidth 50
controlled impedance environment. Figures 1 and 2 show
the top and bottom view of the evaluation board, which can
be configured in several different ways, depending on
device under test (see Table 1. Configuration List).
This evaluation board manual contains:
Information on 32-lead LQFP Evaluation Board
Assembly Instructions
Appropriate Lab Setup
Bill of Materials
This manual should be used in conjunction with the device
data sheet, which contains full technical details on the device
specifications and operation.
Board Lay-Up
The 32-lead LQFP evaluation board is implemented in
four layers with split (dual) power supplies (see Figure 3.
Evaluation Board Lay-Up). For standard ECL lab setup and
test, a split (dual) power supply is essential to enable the 50
internal impedance in the oscilloscope as a termination for
ECL devices. The first layer or primary trace layer is 0.008
thick Rogers RO4003 material, which is designed to have
equal electrical length on all signal traces from the device
under the test (DUT) to the sense output. The second layer
is the 1.0 oz copper ground. The FR4 dielectric material is
placed between second and third layer and between third and
fourth layer. The third layer is the power plane (V
CC
& V
EE
)
and a portion of this layer is a ground plane. The fourth layer
is the secondary trace layer.
Figure 1. Top View of the 32-lead LQFP Evaluation Board
EVALUATION BOARD MANUAL
http://onsemi.com
ECLLQFP32EVB
http://onsemi.com
2
Figure 2. Bottom View of the 32-lead LQFP Evaluation Board
Bottom View
Enlarged Bottom View
Figure 3. Evaluation Board Lay-up
LAY-UP DETAIL
4 LAYER
LAYER 1 (TOP SIDE) 1 OZ
ROGERS 4003 0.008 in
LAYER 2 (GROUND PLANE P1) 1 OZ
FR-4 0.020 in
LAYER 3 (GROUND, VCC & VEE, PLANE P2) 1 OZ
FR-4 0.025 in
LAYER 4 (BOTTOM SIDE) 1 OZ
SILKSCREEN (TOP SIDE)
0.062 0.007
Board Layout
The 32-lead LQFP evaluation board was designed to be
versatile and accommodate several different configurations.
The input, output, and power pin layout of the evaluation
board is shown in Figures 4 and 5. The evaluation board has
at least thirteen possible configurable options. Table 1, list
the devices and the relevant configuration that utilizes this
PCB board. Lists of components and simple schematics are
located in Figures 6 through 18. Place SMA connectors on
J1 through J32, 50 chip resistors between ground pad and
Pin 1 pad through Pin 32 pad, and chip capacitors C1 through
C5 according to configuration figures. (C4 and C5 are 0.01
F and C1, C2, and C3 are 0.1F); (See Figure 5).
ECLLQFP32EVB
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3
Figure 4. Evaluation Board Layout
Top View
Bottom View
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