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Technical Document


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User's Guide
SLAU443May 2012
EEG Front-End Performance Demonstration Kit
This user's guide describes the characteristics, operation, and use of the ADS1299EEG-FE. This EVM is
an evaluation module for the ADS1299, an eight-channel, 24-bit, low-power; integrated analog front-end
(AFE) designed for electroencephalography (EEG) applications. The ADS1299ECG-FE is intended for
prototyping and evaluation. This user's guide includes a complete circuit description, schematic diagram,
and bill of materials.
The following related documents are available through the Texas Instruments web site at www.ti.com.
Device Literature Number
ADS1299 SBAS499
Contents
1 ADS1299EEG-FE Overview ............................................................................................... 4
1.1 Important Disclaimer Information ................................................................................ 4
1.2 Information about Cautions and Warnings ..................................................................... 4
2 Overview ..................................................................................................................... 5
2.1 Introduction ......................................................................................................... 5
2.2 Supported Features ................................................................................................ 5
2.3 Features Not Supported in Current Version .................................................................... 5
2.4 ADS1299EEG-FE Hardware ..................................................................................... 5
2.5 Factory Default Jumper Settings ................................................................................. 6
3 Software Installation ........................................................................................................ 7
3.1 Minimum Requirements ........................................................................................... 7
3.2 Installing the Software ............................................................................................. 7
3.3 Install the ADS1299 EVM Hardware Drivers ................................................................. 10
4 ADS1299EEG-FE Daughter Card Hardware Introduction ........................................................... 13
4.1 Power Supply ..................................................................................................... 14
4.2 Clock ............................................................................................................... 15
4.3 Reference .......................................................................................................... 16
4.4 Accessing ADS1299 Analog Signals .......................................................................... 16
4.5 Accessing ADS1299 Digital Signals ........................................................................... 16
4.6 Analog Inputs ..................................................................................................... 17
5 Using the Software: ADS1299 Control Registers and GUI .......................................................... 18
5.1 Overview and Features .......................................................................................... 18
5.2 Global Channel Registers ....................................................................................... 19
5.3 Channel Control Registers ...................................................................................... 19
5.4 GPIO and Other Registers ...................................................................................... 23
5.5 Lead-Off and BIAS Registers ................................................................................... 23
5.6 Register Map ...................................................................................................... 26
6 ADS1299EEG-FE Analysis Tools ....................................................................................... 27
6.1 Scope Tab ......................................................................................................... 27
6.2 Histogram Tool .................................................................................................... 28
6.3 FFT Tool ........................................................................................................... 29
7 EEG Specific Features .................................................................................................... 32
7.1 Reference Signal and Patient Bias Signal .................................................................... 32
SPI is a trademark of Motorola.
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7.2 Lead-Off Detection ............................................................................................... 36
7.3 External Calibration/Test Signals ............................................................................... 40
8 Test Options on the EVM ................................................................................................. 43
8.1 On Chip (ADS1299) Input Short ................................................................................ 43
8.2 External Input Short with 5K Resistor .......................................................................... 44
8.3 Noise with Common Reference on Negative Inputs ......................................................... 46
8.4 Noise with Buffered Common Reference Input ............................................................... 48
8.5 Internally Generated Test Signal and Other Multiplexer Inputs ............................................ 49
8.6 Arbitrary Input Signal ............................................................................................. 49
9 Bill of Materials, Layouts and Schematics ............................................................................. 50
9.1 ADS1299EEG-FE Front-End Board Schematics ............................................................. 50
9.2 Printed Circuit Board Layout .................................................................................... 53
9.3 Bill of Materials .................................................................................................... 57
9.4 ADS1299EEG-FE Power-Supply Recommendations ....................................................... 59
List of Figures
1 ADS1299EEG-FE Kit ....................................................................................................... 6
2 Executable to Run ADS1299 Software Installation..................................................................... 7
3 Initialization of ADS1299EEG-FE......................................................................................... 8
4 License Agreement ......................................................................................................... 8
5 Installation Process ......................................................................................................... 9
6 USBStyx Driver Preinstallation............................................................................................ 9
7 Completion of ADS1299 Software Installation......................................................................... 10
8 New Hardware Wizard.................................................................................................... 10
9 New Hardware Wizard Screen 3 ........................................................................................ 11
10 Completion of the Initial USB Drive ..................................................................................... 11
11 Second 'New Hardware" Wizard ........................................................................................ 12
12 Install the USBStyx Driver................................................................................................ 12
13 ADS1299 EEG-FE Front End Block Diagram ......................................................................... 14
14 Input Configurations Supported by the EEG-FE a) Differential Inputs b) Single ended inputs.................. 17
15 File Save Option Under 'Save' Tab ..................................................................................... 18
16 Channel Registers GUI for Global Registers .......................................................................... 19
17 Input Multiplexer for a Single Channel (MAIN = [000 or 110 or 111]) .............................................. 20
18 Channel Control Registers GUI Panel.................................................................................. 20
19 Register Bit for SRB1 Routing ........................................................................................... 21
20 Internal Test Signals ...................................................................................................... 21
21 Simplified Diode Arrangement ........................................................................................... 22
22 Eight Channel Read of Internal Temperature Data ................................................................... 22
23 GPIO Control Register GUI Panel....................................................................................... 23
24 LOFF_STATP and LOFF_STATN Comparators ...................................................................... 24
25 LOFF_SENSP and LOFF_SENSN Registers GUI Panel ............................................................ 24
26 Lead-Off Status Indicator................................................................................................. 25
27 BIAS_SENSP and BIAS_SENSN GUI Panel.......................................................................... 26
28 Device Register Settings ................................................................................................. 26
29 Scope Tool Features...................................................................................................... 27
30 Zoom Option on the Waveform Examination Tool .................................................................... 28
31 Histogram Bins for Input Short Noise................................................................................... 29
32 Analysis : FFT Graph of Input Short Test .............................................................................. 30
33 Analysis : FFT : AC Analysis Parameters : Windowing Options .................................................... 31
34 Analysis : FFT : FFT Analysis : Input Short Condition................................................................ 31
35 Changing the User-Defined Dynamic Range for Channel 1 ......................................................... 32
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36 Dedicated Reference and Bias Electrode .............................................................................. 33
37 Programmable reference and bias electrode .......................................................................... 34
38 Settings for Normal Electrode............................................................................................ 35
39 Configuring BIASREF and Bias Drive Buffer .......................................................................... 35
40 Setting up the Bias Drive Loop .......................................................................................... 36
41 Setting the LOFF Register Bits .......................................................................................... 37
42 Configuring the Lead Off Comparator .................................................................................. 37
43 Lead off Status Registers ................................................................................................ 37
44 Scope tab for Impedance Measurement at 31.25Hz ................................................................. 38
45 FFT Analysis for Impedance Measurement at 31.25Hz.............................................................. 39
46 Scope Tab for Impedance Measurement at fDR/4 (DR = 4ksps) ................................................... 40
47 Multiplexer Setting for Calibration with Electrode Disconnected .................................................... 41
48 Multiplexer Setting with Positive Electrode Connected to Test Signal ............................................. 42
49 Multiplexer Setting with Both Electrodes Connected to Test Signal................................................ 42
50 Channel Setting for Input Short Test.................................................................................... 43
51 Global Register Settings for Input Short Test.......................................................................... 43
52 Scope Tab for Input Short Test.......................................................................................... 44
53 Global Register Settings for External Input Short Test ............................................................... 45
54 Scope Showing Noise for Input Short with 5k Resistors ............................................................. 45
55 MISC1 Register Setting for SRB1....................................................................................... 46
56 Noise with Negative Input Connected to SRB1 Pin................................................................... 47
57 Noise with OPA376 in SRB1 Path ...................................................................................... 48
58 Scope Tab with Sinusoidal Inputs on AIN1 ............................................................................ 49
59 ADS1299EEG-FC Schematic ........................................................................................... 50
60 ADS1299EEG-FC Jumper Schematic ................................................................................. 51
61 ECG Power Supplies ..................................................................................................... 52
62 External Reference Drivers (Not Installed) ............................................................................ 53
63 ECG MDK Board Interface Adapter..................................................................................... 53
64 ADS1299EEG-FE Top Assembly ....................................................................................... 54
65 ADS1299EEG-FE Top Layer ............................................................................................ 54
66 ADS1299EEG-FE Internal Layer (1) .................................................................................... 55
67 ADS1299EEG-FE Internal Layer (2) .................................................................................... 55
68 ADS1299EEG-FE Bottom Layer ........................................................................................ 56
69 ADS1299EEG-FE Bottom Assembly.................................................................................... 56
70 Recommended Power Supply for ADS1299EEG-FE................................................................. 59
List of Tables
1 Factory Default Jumper Settings.......................................................................................... 6
2 Power Supply Test Points ................................................................................................ 15
3 Analog Supply Configurations ........................................................................................... 15
4 Digital Supply Configurations ............................................................................................ 15
5 Clock Jumper Options .................................................................................................... 15
6 External Reference Jumper Options .................................................................................... 16
7 Test Signals ................................................................................................................ 16
8 Serial Interface Pin Out................................................................................................... 16
9 Dedicated Reference Drive Options through REF_ELEC............................................................ 33
10 Bill of Materials............................................................................................................. 57
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