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GRM32ER60J107ME20L

Part # GRM32ER60J107ME20L
Description CAP 100UF 6.3VDC X5R 20% SMD1210 - Cut TR (SOS)
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Category CAPACITOR
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Performance Data and Typical Characteristic Curves
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7.14 Thermal Image
Figure 20. Top Board at 12 Vin, 1.5 VDDQ/20 A, No Load at VTT, 25°C Ambient Without Airflow
7.15 DDR3 VDDQ Bode Plot
Figure 21. DDR3 VDDQ Bode Plot at 12 Vin, 1.5 VDDQ/10 A
16
Using the TPS51916EVM-746 Complete DDR2, DDR3, DDR3L, and DDR4 SLUU526 August 2011
Memory Power Solution Synchronous Buck Controller, 2-A LDO, Buffered
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Reference
I
T
EXAS
NSTRUMENTS
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EVM Assembly Drawing and PCB Layout
7.16 DDR3 VTT Bode Plot
Figure 22. DDR3 VTT Bode Plot at 12 Vin, 1.5 VDDQ/0 A and VTT 1-A Sourcing
8 EVM Assembly Drawing and PCB Layout
The following figures (Figure 23 through Figure 28) show the design of the TPS51916EVM-746
printed-circuit board (PCB). The EVM has been designed using a 4-layer, 2-oz copper circuit board.
Figure 23. TPS51916EVM-746 Top Layer Assembly Drawing
17
SLUU526August 2011 Using the TPS51916EVM-746 Complete DDR2, DDR3, DDR3L, and DDR4
Memory Power Solution Synchronous Buck Controller, 2-A LDO, Buffered
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Reference
EVM Assembly Drawing and PCB Layout
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Figure 24. TPS51916EVM-746 Bottom Assembly Drawing
Figure 25. TPS51916EVM-746 Top Copper
18
Using the TPS51916EVM-746 Complete DDR2, DDR3, DDR3L, and DDR4 SLUU526 August 2011
Memory Power Solution Synchronous Buck Controller, 2-A LDO, Buffered
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Reference
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