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GRM32ER60J107ME20L

Part # GRM32ER60J107ME20L
Description CAP 100UF 6.3VDC X5R 20% SMD1210 - Cut TR (SOS)
Additional Information:


Category CAPACITOR
Availability Out of Stock
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Qty Price
1 + $0.13000

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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

CH1:S3
CH2: VTT
Test comdition: 12 VIN, 1.5VDDQ/10 A
0.75 VTT/2 A, VTTREF = 0 A
TPS1916EVM
S3 Enable Shut down
TPS1916EVM
S3 Enable Start up
Test comdition: 12 VIN, 1.5VDDQ/10 A
0.75 VTT/2 A, VTTREF = 0 A
CH1:S3
CH2: VTT
www.ti.com
Performance Data and Typical Characteristic Curves
7.8 S5 Enable Turnon with 1-V Prebias at VDDQ
Figure 12. DDR3 S5 Enable Turnon With 1-V Prebias at VDDQ
7.9 DDR3 S3 Enable Turnon/ Turnoff (S5 is ON)
Figure 13. DDR3 S3 Enable Turnon Figure 14. DDR3 S3 Enable Turnoff
13
SLUU526–August 2011 Using the TPS51916EVM-746 Complete DDR2, DDR3, DDR3L, and DDR4
Memory Power Solution Synchronous Buck Controller, 2-A LDO, Buffered
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Reference
CH1:SW
Test condition: 12 VIN, 1.5VDDQ/20 A
IVTT = 0 A, IVTTREF = 0 A
TPS1916EVM
Switching Node
Performance Data and Typical Characteristic Curves
www.ti.com
7.10 DDR3 VDDQ Output Ripple
Figure 15. DDR3 VDDQ Output Ripple
7.11 DDR3 VDDQ Switching Node
Figure 16. DDR3 VDDQ Switching Node
14
Using the TPS51916EVM-746 Complete DDR2, DDR3, DDR3L, and DDR4 SLUU526– August 2011
Memory Power Solution Synchronous Buck Controller, 2-A LDO, Buffered
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Reference
CH4: 1.5 VDDQ Output Current
Ch1: 1.5 VDDQ Output
Test condition: 12 VIN, 1.5VDDQ/10 A-0 A
IVTT = 0 A, IVTTREF = 0 A
TPS1916EVM
VDDQ Output Transient
From CCM to DCM
CH4: 1.5 VDDQ Output Current
CH1:1.5 VDDQ Output
Test condition: 12 VIN, 1.5VDDQ/0 A-10 A
IVTT = 0 A, IVTTREF = 0 A
TPS1916EVM
VDDQ Output Transient
From DCM to CCM
CH3: VTTREF
Ch1: Sink and Source Transient Signal
CH2: VTT
Test condition: 12 VIN, 1.5VDDQ/0 A
IVTT: Sink 1.5 A and Source 1.5 A
IVTTREF = 0 A
TPS1916EVM
VTT Sink and Source Transient
www.ti.com
Performance Data and Typical Characteristic Curves
7.12 DDR3 VDDQ Output Transient
Figure 17. VDDQ Output Transient From DCM to CCM Figure 18. VDDQ Output Transient From CCM to DCM
7.13 DDR3 VTT Transient With 1.5-A Sinking and Sourcing Current
Figure 19. DDR3 VTT Transient With 1.5-A Sinking and Sourcing Current
15
SLUU526–August 2011 Using the TPS51916EVM-746 Complete DDR2, DDR3, DDR3L, and DDR4
Memory Power Solution Synchronous Buck Controller, 2-A LDO, Buffered
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Reference
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