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GRM32ER60J107ME20L

Part # GRM32ER60J107ME20L
Description CAP 100UF 6.3VDC X5R 20% SMD1210 - Cut TR (SOS)
Additional Information:


Category CAPACITOR
Availability Out of Stock
Qty 0
Qty Price
1 + $0.13000

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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

1.48
1.49
1.5
1.51
1.52
0 2 4 6 8 10 12 14 16 18 20
I - Output Current - A
O
V - Output Voltage - V
O
12 Vin
20 Vin
8 Vin
8 9 10 11 12 13 14
V - Input Voltage - V
I
I = 0 A
O
1.494
1.496
1.498
1.5
1.502
1.504
1.506
V - Output Voltage - V
O
I = 20 A
O
Performance Data and Typical Characteristic Curves
www.ti.com
7.2 DDR3 VDDQ Load Regulation
Figure 5. DDR3 VDDQ Load Regulation
7.3 DDR3 VDDQ Line Regulation
Figure 6. DDR3 VDDQ Line Regulation
10
Using the TPS51916EVM-746 Complete DDR2, DDR3, DDR3L, and DDR4 SLUU526– August 2011
Memory Power Solution Synchronous Buck Controller, 2-A LDO, Buffered
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Reference
0.71
0.72
0.73
0.74
0.75
0.76
0.77
0.78
-2 -1.5 -1 -0.5 0 0.5 1 1.5 2
VTT - Current - A
VTT - Voltage - V
VTT
0.74
0.742
0.744
0.746
0.748
0.75
0.752
0.754
0.756
0.758
0.76
-10 -8 -6 -4 -2 0 2 4 6 8 10
VTTREF - Current - mA
VTTREF
VTTREF - Voltage - V
www.ti.com
Performance Data and Typical Characteristic Curves
7.4 DDR3 VTT Load Regulation
Figure 7. DDR3 VTT Load Regulation
7.5 DDR3 VTTREF Load Regulation
Figure 8. DDR3 VTTREF Load Regulation
11
SLUU526–August 2011 Using the TPS51916EVM-746 Complete DDR2, DDR3, DDR3L, and DDR4
Memory Power Solution Synchronous Buck Controller, 2-A LDO, Buffered
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Reference
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0 0.5 1 1.5 2
VTT - Load Current - A
VTT Dropout Voltage
VTT - Dropout Voltage - V
TPS1916EVM
S5 Enable Shut Down
Test comdition: 12 VIN, 1.5VDDQ/10 A
IVTT = 0 A, VTTREF = 0 A
CH1:S5
CH2: VTTREF
CH3: VDDQ
CH4: PGOOD
TPS1916EVM
S5 Enable Start up
Test comdition: 12 VIN, 1.5VDDQ/10 A
IVTT = 0 A, VTTREF = 0 A
CH1:S5
CH2: VTTREF
CH3: VDDQ
CH4: PGOOD
Performance Data and Typical Characteristic Curves
www.ti.com
7.6 DDR3 VTT Dropout Voltage
Figure 9. DDR3 VTT Dropout Voltage
7.7 DDR3 S5 Enable Turnon/Turnoff
Figure 10. DDR3 S5 Enable Turnon Figure 11. DDR3 S5 Enable Turnoff
12
Using the TPS51916EVM-746 Complete DDR2, DDR3, DDR3L, and DDR4 SLUU526– August 2011
Memory Power Solution Synchronous Buck Controller, 2-A LDO, Buffered
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Reference
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