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SN74LV540ADW

Part # SN74LV540ADW
Description IC INVERTER 8-INPUT 20SOIC
Category IC
Availability In Stock
Qty 956
Qty Price
1 - 200 $0.35589
201 - 401 $0.28309
402 - 602 $0.26691
603 - 803 $0.24804
804 + $0.22108
Manufacturer Available Qty
Texas Instruments
Date Code: 0840
  • Shipping Freelance Stock: 956
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

 
 
  
SCLS409H − APRIL 1998 − REVISED APRIL 2005
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D 2-V to 5.5-V V
CC
Operation
D Max t
pd
of 8.5 ns at 5 V
D Typical V
OLP
(Output Ground Bounce)
<0.8 V at V
CC
= 3.3 V, T
A
= 25°C
D Typical V
OHV
(Output V
OH
Undershoot)
>2.3 V at V
CC
= 3.3 V, T
A
= 25°C
D Support Mixed-Mode Voltage Operation on
All Ports
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE1
A1
A2
A3
A4
A5
A6
A7
A8
GND
V
CC
OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
SN54LV540A ...J OR W PACKAGE
SN74LV540A . . . DB, DGV, DW, NS,
OR PW PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
Y1
Y2
Y3
Y4
Y5
A3
A4
A5
A6
A7
SN54LV540A . . . FK PACKAGE
(TOP VIEW)
A2
A1
OE1
Y7
Y6 OE2
A8
GND
Y8
V
CC
SN74LV540A . . . RGY PACKAGE
(TOP VIEW)
120
10 11
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
A1
A2
A3
A4
A5
A6
A7
A8
Y8
V
GND
CC
OE1
description/ordering information
The ’LV540A devices are octal buffers/drivers designed for 2-V to 5.5-V V
CC
operation.
ORDERING INFORMATION
T
A
PACKAGE
†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QFN − RGY Reel of 1000 SN74LV540ARGYR LV540A
SOIC − DW
Tube of 25 SN74LV540ADW
LV540A
SOIC − DW
Reel of 2000 SN74LV540ADWR
LV540A
SOP − NS Reel of 2000 SN74LV540ANSR 74LV540A
−40°C to 85°C
SSOP − DB Reel of 2000 SN74LV540ADBR LV540A
−40 C to 85 C
Tube of 70 SN74LV540APW
TSSOP − PW
Reel of 2000 SN74LV540APWR
LV540A
TSSOP − PW
Reel of 250 SN74LV540APWT
LV540A
TVSOP − DGV Reel of 2000 SN74LV540ADGVR LV540A
CDIP − J Tube of 20 SNJ54LV540AJ SNJ54LV540AJ
−55°C to 125°C
CFP − W Tube of 85 SNJ54LV540AW SNJ54LV540AW
−55 C to 125 C
LCCC − FK Tube of 55 SNJ54LV540AFK SNJ54LV540AFK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Copyright 2005, Texas Instruments Incorporated
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*%"("'!& *%) % %)$ !( %.' &)#$%& '&') /'))'&0-
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*')'$%%)-
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
 
 
  
SCLS409H − APRIL 1998 − REVISED APRIL 2005
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
These devices are ideal for driving bus lines or buffer memory address registers. They feature inputs and
outputs on opposite sides of the package to facilitate printed circuit board layout.
The 3-state control gate is a two-input AND gate with active-low inputs so that, if either output
enable (OE1
or OE2) input is high, all corresponding outputs are in the high-impedance state. The outputs
provide inverted data when they are not in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE
should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
(each buffer/driver)
INPUTS
OUTPUT
OE1 OE2 A
OUTPUT
Y
L L L H
L LH L
H XX Z
X H X Z
logic diagram (positive logic)
OE1
OE2
To Seven Other Channels
A1
Y1
1
19
2
18
 
 
  
SCLS409H − APRIL 1998 − REVISED APRIL 2005
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
−0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance
or power-off state, V
O
(see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range applied in the high or low state, V
O
(see Notes 1 and 2) −0.5 V to V
CC
+ 0.5 V. . . . . .
Input clamp current, I
IK
(V
I
< 0) −20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 3): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): DGV package 92°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 4): RGY package 37°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
−65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
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