SCES620 – DECEMBER 2004
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
The SN74VMEH22501A 8-bit universal bus transceiver has two integral 1-bit three-wire bus transceivers and
is designed for 3.3-V V
CC
operation with 5-V tolerant inputs. The UBT transceiver allows transparent, latched,
and flip-flop modes of data transfer, and the separate LVTTL input and outputs on the bus transceivers provide
a feedback path for control and diagnostics monitoring. This device provides a high-speed interface between
cards operating at LVTTL logic levels and VME64, VME64x, or VME320
†
backplane topologies.
The SN74VMEH22501A is pin-for-pin capatible to the VMEH22501, but operates at a wider operating
temperature (−40°C to 85°C) range.
High-speed backplane operation is a direct result of the improved OEC circuitry and high drive that has been
designed and tested into the VME64x backplane model. The B-port I/Os are optimized for driving large
capacitive loads and include pseudo-ETL input thresholds (1/2 V
CC
±50 mV) for increased noise immunity.
These specifications support the 2eVME protocols in VME64x (ANSI/VITA 1.1) and 2eSST protocols in
VITA 1.5. With proper design of a 21-slot VME system, a designer can achieve 320-Mbyte transfer rates on
linear backplanes and, possibly, 1-Gbyte transfer rates on the VME320 backplane.
All inputs and outputs are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs.
Active bus-hold circuitry holds unused or undriven 3A-port inputs at a valid logic state. Bus-hold circuitry is not
provided on 1A or 2A inputs, any B-port input, or any control input. Use of pullup or pulldown resistors with the
bus-hold circuitry is not recommended.
This device is fully specified for live-insertion applications using I
off
, power-up 3-state, and BIAS V
CC
. The I
off
circuitry prevents damaging current to backflow through the device when it is powered off/on. The power-up
3-state circuitry places the outputs in the high-impedance state during power up and power down, which
prevents driver conflict. The BIAS V
CC
circuitry precharges and preconditions the B-port input/output
connections, preventing disturbance of active data on the backplane during card insertion or removal, and
permits true live-insertion capability.
When V
CC
is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, output-enable (OE
and OEBY) inputs should be tied
to V
CC
through a pullup resistor and output-enable (OEAB) inputs should be tied to GND through a pulldown
resistor; the minimum value of the resistor is determined by the drive capability of the device connected to this
input.
†
VME320 is a patented backplane construction by Arizona Digital, Inc.
terminal assignments
123456
A 1OEBY NC NC NC NC 1OEAB
B 1Y 1A GND GND V
CC
1B
C 2Y 2A V
CC
V
CC
BIAS V
CC
2B
D 3A1 2OEBY GND GND 2OEAB 3B1
E 3A2 LE V
CC
3B2
F 3A3 OE V
CC
3B3
G 3A4 CLKBA GND GND CLKAB 3B4
H 3A5 3A6 V
CC
V
CC
3B6 3B5
J 3A7 3A8 GND GND 3B8 3B7
K DIR NC NC NC NC V
CC
NC − No internal connection
GQL PACKAGE
(TOP VIEW)
123456
A
B
C
D
E
F
G
H
J
K
