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9TB2

Part # 9TB2
Description
Category TERMINAL
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MARCO
Date Code: 0314
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

REV 1.2.3 4/30/02
Characteristics subject to change without notice.
1 of 25
www.xicor.com
X9259
Quad Digitally-Controlled (XDCP
TM
) Potentiometers
FEATURES
Quad–Four separate potentiometers
256 resistor taps/pot–0.4% resolution
2-Wire Serial Interface for write, read, and
transfer operations of the potentiometer
Wiper Resistance, 100
typical @ V
CC
= 5V
4 Nonvolatile Data Registers for Each
Potentiometer
Nonvolatile Storage of Multiple Wiper Positions
Power On Recall. Loads Saved Wiper Position on
Power Up.
Standby Current < 5µA Max
•V
CC
: 2.7V to 5.5V Operation
50K
, 100K
versions of End to End Pot
Resistance
Endurance: 100,000 Data Changes per Bit per
Register
100 yr. Data Retention
Single Supply Version of X9258
24-Lead SOIC, 24-Lead TSSOP, 24-Lead XBGA
Low Power CMOS
DESCRIPTION
The X9259 integrates 4 digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.
The digital controlled potentiometer is implemented
using 255 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the 2-Wire
bus interface. Each potentiometer has associated with
it a volatile Wiper Counter Register (WCR) and a four
nonvolatile Data Registers that can be directly written
to and read by the user. The contents of the WCR
controls the position of the wiper on the resistor array
though the switches. Powerup recalls the contents of
the default Data Register (DR0) to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
Single Supply / Low Power / 256-tap / 2-Wire bus
A
PPLICATION
N
OTES
AND
D
EVELOPMENT
S
YSTEM
A V A I L A B L E
AN99 • AN115 • AN124 •AN133 • AN134 • AN135
FUNCTIONAL DIAGRAM
R
H0
R
L0
R
W0
V
CC
V
SS
2-Wire
Bus
50K or 100K versions
R
H1
R
L1
R
W1
R
H2
R
L2
R
W2
R
H3
R
L3
R
W3
Power On Recall
Wiper Counter
Registers (WCR)
Data Registers
16 Bytes
Interface
Bus
Interface
and Control
Address
Data
Status
Write
Read
Transfer
Inc/Dec
Control
X9259
Characteristics subject to change without notice.
2 of 25
REV 1.2.3 4/30/02
www.xicor.com
DETAILED FUNCTIONAL DIAGRAM
INTERFACE
AND
CONTROL
CIRCUITRY
A0
SCL
SDA
A1
A2
WP
A3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 1
R
H1
R
L1
Wiper
Counter
Register
(WCR)
R
H0
R
L0
Data
8
R
W0
Resistor
Array
R
H2
R
L2
R
W2
Resistor
Array
R
H3
R
L3
R
W3
Wiper
Counter
Register
(WCR)
Wiper
Counter
Register
(WCR)
Pot 3
Pot 2
Pot 0
V
CC
V
SS
256-taps
50K and 100K
Power On
Recall
Power On
Recall
Power On
Recall
Power On
Recall
DR0
DR1
DR2 DR3
DR0
DR1
DR2 DR3
DR0
DR1
DR2 DR3
DR0
DR1
DR2 DR3
R
W1
CIRCUIT LEVEL APPLICATIONS
Vary the gain of a voltage amplifier
Provide programmable dc reference voltages for
comparators and detectors
Control the volume in audio circuits
Trim out the offset voltage error in a voltage amplifier
circuit
Set the output voltage of a voltage regulator
Trim the resistance in Wheatstone bridge circuits
Control the gain, characteristic frequency and
Q-factor in filter circuits
Set the scale factor and zero point in sensor signal
conditioning circuits
Vary the frequency and duty cycle of timer ICs
Vary the dc biasing of a pin diode attenuator in RF
circuits
Provide a control variable (I, V, or R) in feedback
circuits
SYSTEM LEVEL APPLICATIONS
Adjust the contrast in LCD displays
Control the power level of LED transmitters in
communication systems
Set and regulate the DC biasing point in an RF power
amplifier in wireless systems
Control the gain in audio and home entertainment
systems
Provide the variable DC bias for tuners in RF wireless
systems
Set the operating points in temperature control
systems
Control the operating point for sensors in industrial
systems
Trim offset and gain errors in artificial intelligent
systems
X9259
Characteristics subject to change without notice.
3 of 25
REV 1.2.3 4/30/02
www.xicor.com
PIN CONFIGURATION
PIN ASSIGNMENTS
Note 1:
A0-A3 Device address pins must be tie to a logic level.
Pin
(SOIC/TSSOP)
Pin
(XBGA) Symbol Function
2 F2 A0 Device Address for 2-Wire bus. (See Note 1)
3F1R
W3
Wiper Terminal for Potentiometer 3.
4D2R
H3
High Terminal for Potentiometer 3.
5E1R
L3
Low Terminal for Potentiometer 3.
6 E2 NC1 Must be left unconnected
7C1V
CC
System Supply Voltage
8B1R
L0
Low Terminal for Potentiometer 0.
9C2R
H0
High Terminal for Potentiometer 0.
10 A1 R
W0
Wiper Terminal for Potentiometer 0.
11 A2 A2 Device Address for 2-Wire bus. (See Note 1)
12 B2 WP
Hardware Write Protect
13 B3 SDA Serial Data Input/Output for 2-Wire bus.
14 A3 A1 Device Address for 2-Wire bus. (See Note 1)
15 A4 R
L1
Low Terminal for Potentiometer 1.
16 C3 R
H1
High Terminal for Potentiometer 1.
17 B4 R
W1
Wiper Terminal for Potentiometer 1.
18 C4 V
SS
System Ground
20 E4 R
W2
WiperTerminal for Potentiometer 2.
21 D3 R
H2
High Terminal for Potentiometer 2.
22 F4 R
L2
Low Terminal for Potentiometer 2.
23 F3 SCL Serial Clock for 2-Wire bus.
24 E3 A3 Device Address for 2-Wire Bus. (See Note 1)
6, 19 D1, D4 NC No Connect
1 E2 NC1 Must be left unconnected
NC1
A0
R
W3
NC
V
CC
R
L0
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
15
A3
SCL
R
L2
R
H2
R
W2
NC
V
SS
R
W1
R
H1
R
L1
SOIC/TSSOP
X9259
R
H3
14
13
11
12
R
L3
R
H0
R
W0
A2
A1
SDA
WP
2 3 4
A
B
C
D
E
F
Top View–Bumps Down
R
W0
R
L0
NC
A
0
A3
R
L1
V
CC
R
L3
R
W3
NC1
SDA
R
W1
SCL
R
L2
WP
NC
R
H0
R
H1
R
H3
V
SS
R
W2
A
2
A
1
1
XBGA
R
H2
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