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54-394

Part # 54-394
Description
Category SWITCH
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

P
OUT OUT
1
F =
2 L C´p
Ox
R1x
V = 0.765 V 1+
R2x
æ ö
´
ç ÷
è ø
VINx
12V ± 10%
PGND
1uF
PGND
C
4
SW1
VIN1
VBST1
EN1
VFB2
VFB1
GND
VREG5
PGND1
6
VIN2
VBST2
EN2
SW2
PG1
5
1
3
PG2
9
10
11
PGND2
2
4
7
13
12
TPS54394
HTSSOP16
14
8
15
16
PGND
SGND
SGND
C11
10 Fm
VO1
3.3 V
C21
22 F
x2
m
R11
72.3 kW
R21
22.1 kW
L11
2.2 Hm
C31
0.1 Fm
C32
0.1 Fm
L12
1.5 Hm
C12
10 Fm
VO2
1.5 V
C22
22 F
x2
m
R12
21.5 kW
R22
22.1 kW
TPS54394
www.ti.com
SLVSBE6 JUNE 2012
DESIGN GUIDE
Step By Step Design Procedure
To begin the design process, you must know a few application parameters:
Input voltage range
Output voltage
Output current
In all formulas x is used to indicate that they are valid for both converters. For the calculations the estimated
switching frequency of 700 kHz is used.
Figure 24. Schematic Diagram for the Design Example
Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFBx pin. It is recommended to use
1% tolerance or better divider resistors. Start by using Equation 2 to calculate V
Ox
.
To improve the efficiency at very light loads consider using larger value resistors, but too high resistance values
will be more susceptible to noise and voltage errors due to the VFBx input current will be more noticeable.
(2)
Output Filter Selection
The output filter used with the TPS54394 is an LC circuit. This LC filter has double pole at:
(3)
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( )
Ox INx Ox
COx(RMS)
INx Ox SW
V V V
I =
12 V L
´ -
´ ´ ´ f
2 2
LOx(RMS) Ox L
1
I = I + ΔI
12
L
Lpeakx Ox
ΔI
I = I +
2
INx(MAX) Ox
Ox
L1x
INx(MAX) SW
V V
V
ΔI =
V L1x
-
´
´ f
TPS54394
SLVSBE6 JUNE 2012
www.ti.com
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS545394. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain
rolls off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero
that reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the
zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole
of Equation 3 is located below the high frequency zero but close enough that the phase boost provided by the
high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the
values recommended in Table 1.
Table 1. Recommended Component Values
OUTPUT VOLTAGE (V) R1x (kΩ) R2x (kΩ) Cffx (pF)
(1)
L1x (µH) C2x (µF)
1 6.81 22.1 1.5 - 2.2 20 - 68
1.05 8.25 22.1 1.5 - 2.2 20 - 68
1.2 12.7 22.1 1.5 - 2.2 20 - 68
1.5 21.5 22.1 1.5 - 2.2 20 - 68
1.8 30.1 22.1 5 - 22 2.2 - 3.3 20 - 68
2.5 49.9 22.1 5 - 22 2.2 - 3.3 20 - 68
3.3 73.2 22.1 5 - 22 2.2 - 3.3 20 - 68
5 124 22.1 5 - 22 4.7 20 - 68
6.5 165 22.1 5 - 22 4.7 20 - 68
(1) Optional
For higher output voltages at or above 1.8 V, additional phase boost can be achieved by adding a feed forward
capacitor (Cff) in parallel with R1.
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 4,
Equation 5 and Equation 6. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current.
For the calculations, use 700 kHz as the switching frequency, f
SW
. Make sure the chosen inductor is rated for the
peak current of Equation 5 and the RMS current of Equation 6.
(4)
(5)
(6)
For the above design example, the calculated peak current is 3.46 A and the calculated RMS current is 3.01 A
for VO1. The inductor used is a TDK CLF7045-2R2N with a rated current of 5.5A based on the inductance
change and of 4.3A based on the temperature rise.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS54394 is intended for use
with ceramic or other low ESR capacitors. The recommended value range is from 20µF to 68µF. Use Equation 7
to determine the required RMS current rating for the output capacitor(s).
(7)
For this design two TDK C3216X5R0J226M 22µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.19A and each output capacitor is rated for 4A.
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TPS54394
www.ti.com
SLVSBE6 JUNE 2012
Input Capacitor Selection
The TPS54394 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A ceramic capacitor of or above 10µF is recommended for the decoupling capacitor. Additionally, 0.1
µF ceramic capacitors from pin 1 and Pin 16 to ground are recommended to improve the stability and reduce the
SWx node overshoots. The capacitors voltage rating needs to be greater than the maximum input voltage.
Bootstrap Capacitor Selection
A 0.1 µF ceramic capacitors must be connected between the VBSTx and SWx pins for proper operation. It is
recommended to use ceramic capacitors with a dielectric of X5R or better.
VREG5 Capacitor Selection
A 1 µF ceramic capacitor must be connected between the VREG5 and GND pins for proper operation. It is
recommended to use a ceramic capacitor with a dielectric of X5R or better.
Thermal Information
This 16-pin PWP package incorporates an exposed thermal pad. The thermal pad must be soldered directly to
the printed circuit board (PCB). After soldering, the PCB is used as a heatsink. In addition, through the use of
thermal vias, the thermal pad can be attached directly to the appropriate copper plane shown in the electrical
schematic for the device, or alternatively, can be attached to a special heatsink structure designed into the PCB.
This design optimizes the heat transfer from the integrated circuit (IC).
For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating
abilities, refer to the Technical Brief, PowerPAD™ Thermally Enhanced Package, Texas Instruments Literature
No. SLMA002 and Application Brief, PowerPAD™ Made Easy, Texas Instruments Literature No. SLMA004.
The exposed thermal pad dimensions for this package are shown in the following illustration.
Figure 25. Thermal Pad Dimensions
Layout Considerations
1. Keep the input current loop as small as possible. And avoid the input switching current through the thermal
pad.
2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and
inductance and to minimize radiated emissions.
3. Keep analog and non-switching components away from switching components.
4. Make a single point connection from the signal ground to power ground.
5. Do not allow switching currents to flow under the device.
6. Keep the pattern lines for VINx and PGNDx broad.
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s) :TPS54394
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