SW1
VIN1
VBST1
EN1
VFB2
VFB1
GND
VREG5
PGND1
6
VIN2
VBST2
EN2
SW2
PG1
5
1
3
PG2
9
10
11
PGND2
2
4
7
13
12
14
8
15
16
TPS54394
HTSSOP16
(PowerPAD)
TPS54394
www.ti.com
SLVSBE6 –JUNE 2012
DEVICE INFORMATION
HTSSOP PACKAGE
(TOP VIEW)
PIN FUNCTIONS
(1)
PIN I/O DESCRIPTION
NAME NUMBER
VIN1, VIN2 1, 16 I Power inputs and connects to both high side NFET drains.
Supply Input for 5.5V linear regulator.
VBST1, VBST2 2, 15 I Supply input for high-side NFET gate drive circuit. Connect 0.1µF ceramic capacitor between
VBSTx and SWx pins. An internal diode is connected between VREG5 and VBSTx
SW1, SW2 3, 14 I/O Switch node connections for both the high-side NFETs and low–side NFETs. Input of current
comparator.
PGND1, PGND2 4, 13 I/O Ground returns for low-side MOSFETs. Input of current comparator.
EN1, EN2 5, 12 I Enable. Pull High to enable according converter.
PG1, PG2 6, 11 O Open drain power good output. Low means the output voltage of the corresponding output is
out of regulation.
VFB1, VFB2 7, 10 I D-CAP2 feedback inputs. Connect to output voltage with resistor divider.
GND 8 I/O Signal GND. Connect sensitive SSx and VFBx returns to GND at a single point.
VREG5 9 O Output of 5.5V linear regulator. Bypass to GND with a high-quality ceramic capacitor of at least
1.0 µF. VREG5 is active when ENx is high.
Exposed Thermal Back side I/O Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be
Pad connected to GND.
(1) x means either 1 or 2, e.g. VFBx means VFB1 or VFB2.
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Product Folder Link(s) :TPS54394
