30
MITSUBISHI MICROCOMPUTERS
M37207MF-XXXSP/FP, M37207M8-XXXSP
M37207EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
and ON-SCREEN DISPLAY CONTROLLER
(1) I
2
C Data Shift Register
The I
2
C data shift register (S0 : address 00D916) is an 8-bit shift
register to store receive data and write transmit data.
When transmit data is written into this register, it is transferred to the
outside from bit 7 in synchronization with the SCL clock, and each
time one-bit data is output, the data of this register are shifted one bit
to the left. When data is received, it is input to this register from bit 0
in synchronization with the SCL clock, and each time one-bit data is
input, the data of this register are shifted one bit to the left.
The I
2
C data shift register is in a write enable status only when the
ESO bit of the I
2
C control register (address 00DC16) is “1.” The bit
counter is reset by a write instruction to the I
2
C data shift register.
When both the ESO bit and the MST bit of the I
2
C status register
(address 00F816) are “1,” the SCL is output by a write instruction to
the I
2
C data shift register. Reading data from the I
2
C data shift regis-
ter is always enabled regardless of the ESO bit value.
Note: To write data into the I
2
C data shift register after setting the
MST bit to “0” (slave mode), keep an interval of 8 machine
cycles or more.
Fig. 24. I
2
C Data Shift Register
Fig. 25. I
2
C Address Register
(2) I
2
C Address Register
The I
2
C address register (address 00DA16) consists of a 7-bit slave
___
address and a read/write bit. In the addressing mode, the slave ad-
dress written in this register is compared with the address data to be
received immediately after the START condition are detected.
____
■ Bit 0: Read/Write Bit (RBW)
Not used when comparing addresses, in the 7-bit addressing mode.
In the 10-bit addressing mode, the first address data to be received
is compared with the contents (SAD6 to SAD0 + RBW) of the I
2
C
address register.
The RBW bit is cleared to “0” automatically when the stop condition
is detected.
■ Bits 1 to 7: Slave Address (SAD0–SAD6)
These bits store slave addresses. Regardless of the 7-bit address-
ing mode and the 10-bit addressing mode, the address data trans-
mitted from the master is compared with the contents of these bits.
b7 b6 b5 b4 b3 b2 b1 b0
I C data shift register1(S0) [Address 00D9
16
]
B Functions After reset R W
I C Data Shift Register
0
to
7
This is an 8-bit shift register to store
receive data and write transmit data.
Indeterminate
2
2
Note:
2
To write data into the I C data shift register after setting the MST bit to
“0” (slave mode), keep an interval of 8 machine cycles or more.
Name
D0 to D7
RW
b7 b6 b5 b4 b3 b2 b1 b0
0
Read/write bit
(RBW)
1
to
7
Slave address
(SAD0 to SAD6)
0: Read
1: Write
0
0The address data transmitted from
the master is compared with the
contents of these bits.
I
2
C Address Register
I
2
C address register (S0D) [Address 00DA
16
]
B Name Functions
After reset
RW
R—
RW
