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7207E

Part # 7207E
Description
Category SWITCH
Availability Out of Stock
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

MITSUBISHI MICROCOMPUTERS
M37207MF-XXXSP/FP, M37207M8-XXXSP
M37207EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
and ON-SCREEN DISPLAY CONTROLLER
10
R, G, B, I, OUT,

H
SYNC, VSYNC
Internal circuit
Internal circuit
Fig. 2. I/O Pin Block Diagram (2)
Schmidt input
HSYNC, VSYNC
CMOS output
P52–P55, φ
Note : Each port is also used as follows:
P52 : R
P53 : G
P54 : B
P55 : I/TIM1
P56 : OUT
P52–P55, φ
MITSUBISHI MICROCOMPUTERS
M37207MF-XXXSP/FP, M37207M8-XXXSP
M37207EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
and ON-SCREEN DISPLAY CONTROLLER
11
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
This microcomputer uses the standard 740 Family instruction set.
Refer to the table of 740 Family addressing modes and machine
instructions or the SERIES 740 <Software> User’s Manual for de-
tails on the instruction set.
Machine-resident 740 Family instructions are as follows:
The FST, SLW instruction cannot be used.
The MUL, DIV, WIT and STP instructions can be used.
CPU Mode Register
The CPU mode register contains the stack page selection bit and
internal system clock selection bit. The CPU mode register is allo-
cated at address 00FB16.
Fig. 3. CPU Mode Register
b7b6 b5b4b3 b2b1b0
B
After reset
RW
CPU Mode Register
0, 1
2
3
0
1
Name Functions
Processor mode bits
(CM0, CM1)
0 0: Single-chip mode
0 1:
1 0: Not available
1 1:
Fix these bits to “1.”
1
Stack page selection
bit (CM2) (See note 1)
1
b1 b0
0: 0 page
1: 1 page
00
CPU mode register (CPUM) (CM) [Address 00FB
16
]
RW
RW
RW
51
60
Main Clock (X
IN
–X
OUT
)
stop bit
(CM6)
RW
RW
X
COUT
drivability
selection bit (CM5)
0: LOW drive
1: HIGH drive
0: Oscillating
1: Stopped
70
Internal system clock
selection bit
(CM7)
RW
0: X
IN
–X
OUT
selected
(high-speed mode)
1: X
CIN
–X
COUT
selected
(high-speed mode)
Notes 1: This bit is set to “1” after the reset release.
2: The internal system clock
φ
stops at HIGH.
41
Internal system clock
output selection bit
(CM4) (See note 2)
0: Output is stopped
1: Internal system
clock
φ
output
RW
MITSUBISHI MICROCOMPUTERS
M37207MF-XXXSP/FP, M37207M8-XXXSP
M37207EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
and ON-SCREEN DISPLAY CONTROLLER
12
MEMORY
Special Function Register (SFR) Area
The special function register (SFR) area in the zero page contains
control registers such as I/O ports and timers.
RAM
RAM is used for data storage and for stack area of subroutine calls
and interrupts.
ROM
ROM is used for storing user programs as well as the interrupt vector
area.
RAM for Display
RAM for display is used for specifying the character codes and col-
ors to display.
ROM for Display
ROM for display is used for storing character data.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
Zero Page
The 256 bytes from addresses 000016 to 00FF16 are called the zero
page area. The internal RAM and the special function registers (SFR)
are allocated to this area.
The zero page addressing mode can be used to specify memory and
register addresses in the zero page area. Access to this area with
only 2 bytes is possible in the zero page addressing mode.
Special Page
The 256 bytes from addresses FF0016 to FFFF16 are called the spe-
cial page area. The special page addressing mode can be used to
specify memory addresses in the special page area. Access to this
area with only 2 bytes is possible in the special page addressing
mode.
Fig. 4. Memory Map
ROM Correction Memory (RAM)
This is used as the program area for ROM correction.
000016
00C016
00FF16
01FF16
033F16
080016
SFR area
Not used
Not used
FFFF
16
FFDE16
FF0016
030016
Interrupt vector area
Not used
10000
16
11FFF16
1FFFF16
ROM
for display
(8 K bytes)
for M37207M8
Special page
ROM
(32 K bytes)
for M37207M8
RAM
for display
(144 bytes)
(See note)
Zero page
Note: Refer to Table 9. Contents of CRT display RAM.
020416
021B16
02C016
02FF16
2 page register
Not used
06D716
060016
Not used
ROM correction memory (64 bytes)
Block 1: addresses 02C0
16 to 02DF16
Block 2: addresses 02E016 to 02FF16
800016
04FF16
12FFF16
ROM
for display
(12 K bytes)
for M37207MF
ROM
(62 K bytes)
for M37207MF
RAM
(512 bytes)
for M37207M8
RAM
(960 bytes)
for M37207MF
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