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7207E

Part # 7207E
Description
Category SWITCH
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

MITSUBISHI MICROCOMPUTERS
M37207MF-XXXSP/FP, M37207M8-XXXSP
M37207EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
and ON-SCREEN DISPLAY CONTROLLER
73
Fig. 70. Interrupt Interval Determination Control Register
INT1 or INT2 input
Count interval
Fig. 71. Measuring Interval
b7 b6 b5 b4 b3 b2 b1 b0
interrupt interval determination control register (RE) [Address 00D8
16
]
B Name Functions
After reset
R
W
Interrupt Interval Determination Control Register
0 Interrupt interval
determination circuit
operation control bit (RE0)
0 : Stopped
1 : Operating
0
1 Reference clock selection
bit (RE1)
0 : 16 µs
1 : 32 µs
(at f(X
IN
) = 8 MHz)
0
2 External interrupt input
pin selection bit (RE2)
0 : INT1 input
1 : INT2 input
0
3 INT1 pin input polarity
switch bit (RE3)
0 : Positive polarity input
1 : Negative polarity input
0
4 INT2 pin input polarity
switch bit (RE4)
0 : Positive polarity input
1 : Negative polarity input
0
5
to
7
0
RW
RW
RW
RW
RW
R—
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
MITSUBISHI MICROCOMPUTERS
M37207MF-XXXSP/FP, M37207M8-XXXSP
M37207EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
and ON-SCREEN DISPLAY CONTROLLER
74
ROM CORRECTION FUNCTION
This can correct program data in ROM. Up to 2 addresses (2 blocks)
can be corrected, a program for correction is stored in the ROM cor-
rection memory in RAM. The ROM memory for correction is 32 bytes
2 blocks.
Block 1 : addresses 02C016 to 02DF16
Block 2 : addresses 02E016 to 02FF16
Set the address of the ROM data to be corrected into the ROM cor-
rection address register. When the value of the counter matches the
ROM data address in the ROM correction address, the main pro-
gram branches to the correction program stored in the ROM memory
for correction. To return from the correction program to the main pro-
gram, the op code and operand of the JMP instruction (total of 3
bytes) are necessary at the end of the correction program. When the
blocks 1 and 2 are used in series, the above instruction is not needed
at the end of the block 1.
The ROM correction function is controlled by the ROM correction
enable register.
Notes 1 : Specify the first address (op code address) of each
instruction as the ROM correction address.
2 : Use the JMP instruction (total of 3 bytes) to return from
the correction program to the main program.
3 : Do not set the same ROM correction address to the blocks
1 and 2.
Fig. 72. ROM Correction Address Registers
Fig. 73. ROM Correction Enable Register
0217
16
ROM correction address 1 (high-order)
0218
16
ROM correction address 1 (low-order)
0219
16
ROM correction address 2 (high-order)
021A
16
ROM correction address 2 (low-order)
b7 b6 b5 b4 b3 b2 b1 b0
ROM correction enable register (RCR) [Address 021B16]
B
After reset
RW
ROM Correction Enable Register
0 Block 1 enable bit (RC0)
Name Functions
0: Disabled
1: Enabled
1 Block 2 enable bit (RC1) 0: Disabled
1: Enabled
4
to
7
Nothing is assigned. These bits are write disable bits. When
these bits are read out, the values are “0.”
0
0
0
RW
RW
R—
00
2, 3
Fix these bits to“0.”
0
RW
MITSUBISHI MICROCOMPUTERS
M37207MF-XXXSP/FP, M37207M8-XXXSP
M37207EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
and ON-SCREEN DISPLAY CONTROLLER
75
Power source voltage 0 V
Reset input voltage 0 V
4.5 V
0.6 V
Poweron
Vcc
RESET
Vss
Microcomputer
1
5
4
3
0.1µF
M51953AL
RESET CIRCUIT
When the oscillation of a quartz-crystal oscillator or a ceramic reso-
nator is stable and the power source voltage is 5 V ± 10 %, hold the
______
RESET pin at LOW for 2 µs or more, then return is to HIGH. Then, as
shown in Figure 75, reset is released and the program starts from
the address formed by using the content of address FFFF16 as the
high-order address and the content of the address FFFE16 as the
low-order address. The internal state of microcomputer at reset are
shown in Figure 75.
An example of the reset circuit is shown in Figure 74.
The reset input voltage must be kept 0.6 V or less until the power
source voltage surpasses 4.5 V.
Fig. 74. Example of Reset Circuit
Fig. 75. Reset Sequence
XIN
φ
RESET
Internal RESET
SYNC
Address
Data
32768 count of XIN
clock cycle (Note 3)
Reset address from the vector table
? ?
01, S
01, S-1
01, S-2
FFFE FFFF
ADH,
ADL
? ? ? ? ?
ADL ADH
Notes 1 :
:
:
f(XIN) and f(φ) are in the relation : f(XIN) = 2·f (φ).
2 A question mark (?) indicates an undefined state that
depends on the previous state.
3
Immediately after a reset, timer 3 and timer 4 are
connected by hardware. At this time, “FF
16” is set
in timer 3 and “07
16” is set to timer 4. Timer 3 counts down
with f(X
IN)/16, and reset state is released by the timer 4
overflow signal.
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