MITSUBISHI MICROCOMPUTERS
M37207MF-XXXSP/FP, M37207M8-XXXSP
M37207EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
and ON-SCREEN DISPLAY CONTROLLER
39
PWM OUTPUT FUNCTION
This microcomputer is equipped with a 14-bit PWM (DA) and ten 8-
bit PWMs (PWM0–PWM9). DA has a 14-bit resolution with the mini-
mum resolution bit width of 250 ns and a repeat period of
4096 µs (for f(XIN) = 8 MHz). PWM0–PWM9 have the same circuit
structure and an 8-bit resolution with minimum resolution bit width of
4 µs and repeat period of 1024 µs (for f(XIN) = 8 MHz).
Figure 35 shows the PWM block diagram. The PWM timing generat-
ing circuit applies individual control signals to PWM0–PWM9 using
f(XIN) divided by 2 as a reference signal.
(1) Data Setting
When outputting DA, first set the high-order 8 bits to the DA-H regis-
ter (address 00CE16), then the low-order 6 bits to the DA-L register
(address 00CF16). When outputting PWM0–PWM9, set 8-bit output
data to the PWMi register (i means 0 to 9; addresses 00D016 to
00D416, 00F616 to 00FA16).
(2) Transferring Data from Registers to Latches
The data written to the 8-bit PWM register is transferred to the PWM
latch in each 8-bit PWM cycle period. For 14-bit PWM, the data is
transferred in the next high-order 8-bit period after the write. The
signals output to the PWM pins correspond to the contents of these
latches. When data in each PWM register is read, data in these
latches has already been read allowing the data output by the PWM
to be confirmed. However, bit 7 of the DA-L register indicated the
completion of the data transfer from the DA register to the DA latch.
When bit 7 is “0,” the transfer has been completed. When bit 7 is “1,”
the transfer has not yet begun.
(3) Operating of 8-bit PWM
The following explains PWM operation.
First, set the bit 0 of PWM output control register 1 (address 00D516)
to “0” (at reset, bit 0 is already set to “0” automatically), so that the
PWM count source is supplied.
PWM0–PWM7 are also used as pins P60–P67, PWM8, PWM9 are
also used as ports pins P47, P46, respectively. For PWM0–PWM9,
set the corresponding bits of the ports P4 or P6 direction register to
“1” (output mode). And select each output polarity by bit 3 of PWM
output control register 2(address 00D616). Then, for PWM0–PWM5,
set bits 2 to 7 of PWM output control register 1 to “1” (PWM output).
For PWM6 and PWM7, set bits 0 and 1 of the PWM output control
register 2 to “1.” For PWM8 and PWM9, set bits 3, 6 and 7 of the
serial I/O control register to “1.”
The PWM waveform is output from the PWM output pins by setting
these registers.
Figure 36 shows the 8-bit PWM timing. One cycle (T) is composed
of 256 (2
8
) segments. The 8 kinds of pulses, relative to the weight of
each bit (bits 0 to 7), are output inside the circuit during 1 cycle.
Refer to Figure 36 (a). The 8-bit PWM outputs waveform which is
the logical sum (OR) of pulses corresponding to the contents of bits
0 to 7 of the 8-bit PWM register. Several examples are shown in
Figure 36 (b). 256 kinds of output (HIGH area: 0/256 to 255/256) are
selected by changing the contents of the PWM register. A length of
entirely HIGH output cannot be output, i.e. 256/256.
(4) Operating of 14-bit PWM
As with 8-bit PWM, set the bit 0 of PWM output control register 1
(address 00D516) to “0” (at reset, bit 0 is already set to “0” automati-
cally), so that the PWM count source is supplied. Next, select the
output polarity by bit 2 of PWM output control register 2 (address
00D616). Then, the 14-bit PWM outputs from the D-A output pin by
setting bit 1 of PWM output control register 1 to “0” (at reset, this bit
already set to “0” automatically) to select the DA output.
The output example of the 14-bit PWM is shown in Figure 37.
The 14-bit PWM divides the data of the DA latch into the low-order 6
bits and the high-order 8 bits.
The fundamental waveform is determined with the high-order 8-bit
data “DH.” A HIGH area with a length τ ✕ DH (HIGH area of funda-
mental waveform) is output every short area of “t” = 256τ =
64 µs (τ is the minimum resolution bit width of 250 ns). The “H” level
area increase interval (tm) is determined with the low-order 6-bit data
“DL.” The HIGH are of smaller intervals “tm” shown in Table 5 is longer
by τ than that of other smaller intervals in PWM repeat period “T” =
64t. Thus, a rectangular waveform with the different HIGH width is
output from the D-A pin. Accordingly, the PWM output changes by τ
unit pulse width by changing the contents of the DA-H and DA-L
registers. A length of entirely HIGH cannot be output, i. e. 256/256.
(5) Output after Reset
At reset, the output of ports P60–P67, P46 and P47 are in the high-
impedance state, and the contents of the PWM register and the
PWM circuit are undefined. Note that after reset, the PWM output is
undefined until setting the PWM register.
