Name: 7207E
SKU: 7207E

MITSUBISHI MICROCOMPUTERS

M37207MF-XXXSP/FP, M37207M8-XXXSP

M37207EFSP/FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

and ON-SCREEN DISPLAY CONTROLLER

■ Bit 5: Bus Busy Flag (BB)

This bit indicates the status of use of the bus system. When this bit is

set to “0,” this bus system is not busy and a START condition can be

generated. When this bit is set to “1,” this bus system is busy and the

occurrence of a START condition is disabled by the START condi-

tion duplication prevention function (Note).

This flag can be written by software only in the master transmission

mode. In the other modes, this bit is set to “1” by detecting a START

condition and set to “0” by detecting a STOP condition. When the

ESO bit of the I

C control register (address 00DC16) is “0” and at

reset, the BB flag is kept in the “0” state.

■ Bit 6: Communication Mode Specification Bit (transfer direction

specification bit: TRX)

This bit decides the direction of transfer for data communication. When

this bit is “0,” the reception mode is selected and the data of a trans-

mitting device is received. When the bit is “1,” the transmission mode

is selected and address data and control data are output into the

SDA in synchronization with the clock generated on the SCL.

When the ALS bit of the I

C control register (address 00DC16) is “0”

in the slave reception mode is selected, the TRX bit is set to “1”

(transmit) if the least significant bit (R/W bit) of the address data trans-

mitted by the master is “1.” When the ALS bit is “0” and the R/W bit is

“0,” the TRX bit is cleared to “0” (receive).

The TRX bit is cleared to “0” in one of the following conditions.

•

When arbitration lost is detected.

•

When a STOP condition is detected.

•

When occurence of a START condition is disabled by the START

condition duplication prevention function (Note).

•

With MST = “0” and when a START condition is detected.

•

With MST = “0” and when ACK non-return is detected.

•

At reset

■ Bit 7: Communication Mode Specification Bit (master/slave speci-

fication bit: MST)

This bit is used for master/slave specification for data communica-

tion. When this bit is “0,” the slave is specified, so that a START

condition and a STOP condition generated by the master are received,

and data communication is performed in synchronization with the

clock generated by the master. When this bit is “1,” the master is

specified and a START condition and a STOP condition are gener-

ated, and also the clocks required for data communication are gen-

erated on the SCL.

The MST bit is cleared to “0” in one of the following conditions.

•

Immediately after completion of 1-byte data transmission when ar-

bitration lost is detected

•

When a STOP condition is detected.

•

When occurence of a START condition is disabled by the START

condition duplication preventing function (Note).

•

At reset

Note: The START condition duplication prevention function disables

the START condition generation, reset of bit counter reset,

and SCL output, when the following condition is satisfied:

• a START condition is set by another master device.

MITSUBISHI MICROCOMPUTERS

M37207MF-XXXSP/FP, M37207M8-XXXSP

M37207EFSP/FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

and ON-SCREEN DISPLAY CONTROLLER

Fig. 30. Interrupt Request Signal Generation Timing

Fig. 29. I

C Status Register

SCL

IICIRQ

b7 b6 b5 b4 b3 b2 b1 b0

C status register (S1) [Address 00DB

]

C Status Register

6, 7 b7 b6

0 0 : Slave recieve mode

0 1 : Slave transmit mode

1 0 : Master recieve mode

1 1 : Master transmit mode

B Name Functions

After reset

Communication mode

specification bits

(TRX, MST)

0 : Bus free

1 : Bus busy

Bus busy flag (BB)

0 : Interrupt request issued

1 : No interrupt request issued

C-BUS interface interrupt

request bit (PIN)

0 : Not detected

1 : Detected

Arbitration lost detecting flag

(AL) (See note)

0 : Address mismatch

1 : Address match

Slave address comparison

flag (AAS) (See note)

0 : No general call detected

1 : General call detected

General call detecting flag

(AD0) (See note)

0 : Last bit = “0 ”

1 : Last bit = “1 ”

Last receive bit (LRB)

(See note)

Note : These bits and flags can be read out, but cannnot be written.

Indeterminate

R—

MITSUBISHI MICROCOMPUTERS

M37207MF-XXXSP/FP, M37207M8-XXXSP

M37207EFSP/FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

and ON-SCREEN DISPLAY CONTROLLER

(9) START/STOP Condition Detect Conditions

The START/STOP condition detect conditions are shown in

Figure 33 and Table 4. Only when the 3 conditions of Table 4 are

satisfied, a START/STOP condition can be detected.

Note: When a STOP condition is detected in the slave mode

(MST = 0), an interrupt request signal “IICIRQ” is generated

to the CPU.

(8) STOP Condition Generation Method

When the ES0 bit of the I

C control register (address 00DC16) is “1,”

execute a write instruction to the I

C status register (address 00DB16)

for setting the MST bit and the TRX bit to “1” and the BB bit to “0”. A

STOP condition will then be generated. The STOP condition genera-

tion timing and the BB flag reset timing are different in the standard

clock mode and the high-speed clock mode. Refer to Figure 32 for

the STOP condition generation timing diagram, and Table 3 for the

START condition/STOP condition generation timing table.

Fig. 32. STOP Condition Generation Timing Diagram

Fig. 33. START Condition/STOP Condition Detect Timing

Diagram

Table 4. START Condition/STOP Condition Detect Conditions

Table 3. START Condition/STOP Condition Generation Timing

Table

Item

Setup time

Hold time

Set/reset time

for BB flag

Standard Clock Mode

5.0 µs (20 cycles)

3.0 µs (12 cycles)

High-speed Clock Mode

2.5 µs (10 cycles)

1.5 µs (6 cycles)

Note: Absolute time at φ = 4 MHz. The value in parentheses de-

notes the number of φ

cycles.

C status register

write signal

Reset time for

BB flag

Hold time

Setup

time

SCL

SDA

BB flag

Hold time

Setup

time

SCL

SDA

(START condition)

SDA

(STOP condition)

SCL release time

Hold time

Setup

time

(6) START Condition Generation Method

When the ESO bit of the I

C control register (address 00DC16) is “1,”

execute a write instruction to the I

C status register (address 00DB16)

to set the MST, TRX and BB bits to “1.” A START condition will then

be generated. After that, the bit counter becomes “0002” and an SCL

for 1 byte is output. The START condition generation timing and BB

bit set timing are different in the standard clock mode and the high-

speed clock mode. Refer to Figure 31 for the START condition gen-

eration timing diagram, and Table 3 for the START condition/STOP

condition generation timing table.

Fig. 31. START Condition Generation Timing Diagram

(7) RESTART Condition Generation Method

To generate the RESTART condition, take the following sequence:

Set “2016” to the I

C status register (S1).

Write a transmit data to the I

C data shift register.

Set “F016” to the I

C status register (S1) again.

C status register ; S1 = 2016

C data shift register ; S0 = transmit data after restart

C status register ; S1 = F016

C status register

write signal

Set time for

BB flag

Hold time

Setup

time

SCL

SDA

BB flag

Setup

time

Standard Clock Mode

6.5 µs (26 cycles) <

SCL

release time

3.25 µs (13 cycles) < Setup time

3.25 µs (13 cycles) < Hold time

High-speed Clock Mode

1.0 µs (4 cycles) <

SCL

release time

0.5 µs (2 cycles) < Setup time

0.5 µs (2 cycles) < Hold time

Note: Absolute time at φ = 4 MHz. The value in parentheses de-

notes the number of φ cycles.

Part #	7207E
Description
Category	SWITCH
Availability	Out of Stock
Qty	0

7207E

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Technical Document