Name: 7207E
SKU: 7207E

MITSUBISHI MICROCOMPUTERS

M37207MF-XXXSP/FP, M37207M8-XXXSP

M37207EFSP/FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

and ON-SCREEN DISPLAY CONTROLLER

(3) I

C Clock Control Register

The I

C clock control register (address 00DD16) is used to set ACK

control, SCL mode and SCL frequency.

■ Bits 0 to 4: SCL Frequency Control Bits (CCR0–CCR4)

These bits control the SCL frequency. Refer to Figure 26.

■ Bit 5: SCL Mode Specification Bit (FAST MODE)

This bit specifies the SCL mode. When this bit is set to “0,” the stan-

dard clock mode is set. When the bit is set to “1,” the high-speed

clock mode is set.

■ Bit 6: ACK Bit (ACK BIT)

This bit sets the SDA status when an ACK clock

✽

is generated. When

this bit is set to “0,” the ACK return mode is set and SDA goes to

LOW at the occurrence of an ACK clock. When the bit is set to “1,”

the ACK non-return mode is set. The SDA is held in the HIGH status

at the occurrence of an ACK clock.

However, when the slave address matches the address data in the

reception of address data at ACK BIT = “0,” the SDA is automatically

made LOW (ACK is returned). If there is a mismatch between the

slave address and the address data, the SDA is automatically made

HIGH (ACK is not returned).

✽ ACK clock: Clock for acknowledgement

■ Bit 7: ACK Clock Bit (ACK)

This bit specifies a mode of acknowledgment which is an acknowl-

edgment response of data transmission. When this bit is set to “0,”

the no ACK clock mode is set. In this case, no ACK clock occurs

after data transmission. When the bit is set to “1,” the ACK clock

mode is set and the master generates an ACK clock upon comple-

tion of each 1-byte data transmission.The device for transmitting

address data and control data releases the SDA at the occurrence of

an ACK clock (make SDA HIGH) and receives the ACK bit gener-

ated by the data receiving device.

Note: Do not write data into the I

C clock control register during

transmission. If data is written during transmission, the I

clock generator is reset, so that data cannot be transmitted

normally.

Fig. 26. I

C Clock Control Register

b7 b6 b5 b4 b3 b2 b1 b0

C clock control register (S2 : address 00DD

)

C Clock Control Register

SCL frequency control bits

(CCR0 to CCR4)

SCL mode

specification bit

(FAST MODE)

0 : Standard clock mode

1 : High-speed clock mode

Standard clock

mode

B Name Functions

After reset

ACK bit

(ACK BIT)

ACK clock bit

(ACK)

0 : ACK is returned.

1 : ACK is not returned.

0 : No ACK clock

1 : ACK clock

High speed

clock mode

Setup disabled Setup disabled

00 to 02

Setup disabled

33303

Setup disabled

25004

100

400 (See note)

83.3 16606

500/CCR value 1000/CCR value

...

17.2 34.5

16.6 33.3

16.1

32.3

(at

= 4 MHz, unit : kHz)

Note: At 400 kHz in the high-speed clock mode, the duty is as below .

“0” period : “1” period = 3 : 2

In the other cases, the duty is as below.

“0” period : “1” period = 1 : 1

Setup value of

CCR4–CCR0

MITSUBISHI MICROCOMPUTERS

M37207MF-XXXSP/FP, M37207M8-XXXSP

M37207EFSP/FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

and ON-SCREEN DISPLAY CONTROLLER

(4) I

C Control Register

The I

C control register (address 00DC16) controls the data commu-

nication format.

■ Bits 0 to 2: Bit Counter (BC0–BC2)

These bits decide the number of bits for the next 1-byte data to be

transmitted. An interrupt request signal occurs immediately after the

number of bits specified with these bits are transmitted.

When a START condition is received, these bits become “0002” and

the address data is always transmitted and received in 8 bits.

■ Bit 3: I

C Interface Use Enable Bit (ESO)

This bit enables usage of the multimaster I

C BUS interface. When

this bit is set to “0,” the use disable status is provided, so the SDA

and the SCL become high-impedance. When the bit is set to “1,” use

of the interface is enabled.

When ESO = “0,” the following is performed.

•

PIN = “1,” BB = “0” and AL = “0” are set (they are bits of the I

status register at address 00F816 ).

•

Writing data to the I

C data shift register (address 00F616) is dis-

abled.

■ Bit 4: Data Format Selection Bit (ALS)

This bit decides whether or not to recognize slave addresses. When

this bit is set to “0,” the addressing format is selected, so that ad-

dress data is recognized. When a match is found between a slave

address and address data as a result of comparison or when a gen-

eral call (refer to “(5) I

C Status Register,” bit 1) is received, trans-

mission processing can be performed. When this bit is set to “1,” the

free data format is selected, so that slave addresses are not recog-

nized.

Fig. 28. I

C Control Register

■ Bit 5: Addressing Format Selection Bit (10BIT SAD)

This bit selects a slave address specification format. When this bit is

set to “0,” the 7-bit addressing format is selected. In this case, only

the high-order 7 bits (slave address) of the I

C address register (ad-

dress 00F716) are compared with address data. When this bit is set

to “1,” the 10-bit addressing format is selected, all the bits of the I

address register are compared with address data.

■

Bits 6 and 7: Connection Control Bits between I

C-BUS Interface

and Ports (BSEL0, BSEL1)

These bits controls the connection between SCL and ports or SDA

and ports (refer to Figure 28).

Fig. 27. Connection Port Control by BSEL0 and BSEL1

“0”

“1” BSEL0

“0”

“1” BSEL1

SCL1/P4

SCL2/P4

Multi-master

C-BUS

interface

SCL

SDA

SCL3/P4

“0”

“1”

CIIC (Note 2)

“0”

“1” BSEL0

“0”

“1” BSEL1

SDA1/P4

SDA2/P4

SDA3/P4

“0”

“1”

CIIC (Note 2)

Notes 1 : When using multi-master I

C-BUS interface, set bits 3 to

7 of the serial I/O mode register (address 00DE16) to “1.”

2 : CIIC is bit 2 of the serial I/O control register (address

020716) (refer to Figure 21).

b7 b6 b5 b4 b3 b2 b1 b0

Bit counter

(Number of transmit/recieve

bits)

(BC0 to BC2)

b2 b1 b0

0 0 0 : 8

0 0 1 : 7

0 1 0 : 6

0 1 1 : 5

1 0 0 : 4

1 0 1 : 3

1 1 0 : 2

1 1 1 : 1

C-BUS interface use

enable bit (ESO)

0 : Disabled

1 : Enabled

4 Data format selection bit

(ALS)

0 : Addressing mode

1 : Free data format

Addressing format selection

bit (10BIT SAD)

0 : 7-bit addressing format

1 : 10-bit addressing format

6, 7 Connection control bits

between I C-BUS interface

and ports

b7 b6 Connection port (See note)

0 0 : None

0 1 : SCL1, SDA1

1 0 : SCL2, SDA2

1 1 : SCL1, SDA1

SCL2, SDA2

C control register (S1D : address 00DC

)

C Control Register

B Name Functions

After reset

Note: When using ports P1

-P1

as I C-BUS interface, the output structure changes

automatically from CMOS output to N-channel open-drain output.

MITSUBISHI MICROCOMPUTERS

M37207MF-XXXSP/FP, M37207M8-XXXSP

M37207EFSP/FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

and ON-SCREEN DISPLAY CONTROLLER

(5) I

C Status Register

The I

C status register (address 00DB16) controls the I

C-BUS inter-

face status. The low-order 4 bits are read-only bits and the high-

order 4 bits can be read out and written to.

■

Bit 0: Last Receive Bit (LRB)

This bit stores the last bit value of received data and can also be

used for ACK receive confirmation. If ACK is returned when an ACK

clock occurs, the LRB bit is set to “0.” If ACK is not returned, this bit

is set to “1.” Except in the ACK mode, the last bit value of received

data is input. The state of this bit is changed from “1” to “0” by execut-

ing a write instruction to the I

C data shift register (address 00D916).

■ Bit 1: General Call Detecting Flag (AD0)

This bit is set to “1” when a general call

✽

whose address data is all “0”

is received in the slave mode. By a general call of the master device,

every slave device receives control data after the general call. The

AD0 bit is set to “0” by detecting the STOP condition or START con-

dition.

✽ General call: The master transmits the general call address “0016”

to all slaves.

■ Bit 2: Slave Address Comparison Flag (AAS)

This flag indicates a comparison result of address data.

In the slave receive mode, when the 7-bit addressing format is

selected, this bit is set to “1” in one of the following conditions.

•

The address data immediately after occurrence of a START

condition matches the slave address stored in the high-order

7 bits of the I

C address register (address 00DA16).

•

A general call is received.

In the slave reception mode, when the 10-bit addressing format is

selected, this bit is set to “1” with the following condition.

•

When the address data is compared with the I

C address

bytes match.

The state of this bit is changed from “1” to “0” by executing a write

instruction to the I

C data shift register (address 00D916).

■ Bit 3: Arbitration Lost

✽

Detecting Flag (AL)

In the master transmission mode, when a device other than the mi-

crocomputer sets the SDA to “L,”, arbitration is judged to have been

lost, so that this bit is set to “1.” At the same time, the TRX bit is set to

“0,” so that immediately after transmission of the byte whose arbitra-

tion was lost is completed, the MST bit is set to “0.” When arbitration

is lost during slave address transmission, the TRX bit is set to “0”

and the reception mode is set. Consequently, it becomes possible to

receive and recognize its own slave address transmitted by another

master device.

✽ Arbitration lost: The status in which communication as a master is

disabled.

■ Bit 4: I

C-BUS Interface Interrupt Request Bit (PIN)

This bit generates an interrupt request signal. Each time 1-byte data

is transmitted, the state of the PIN bit changes from “1” to “0.” At the

same time, an interrupt request signal is sent to the CPU. The PIN bit

is set to “0” in synchronization with a falling edge of the last clock

(including the ACK clock) of an internal clock and an interrupt re-

quest signal occurs in synchronization with a falling edge of the PIN

bit. When the PIN bit is “0,” the SCL is kept in the “0” state and clock

generation is disabled. Figure 30 shows an interrupt request signal

generating timing chart.

The PIN bit is set to “1” in any one of the following conditions.

•

Executing a write instruction to the I

C data shift register (address

00F616).

•

When the ESO bit is “0”

•

At reset

The conditions in which the PIN bit is set to “0” are shown below:

•

Immediately after completion of 1-byte data transmission (includ-

ing when arbitration lost is detected)

•

Immediately after completion of 1-byte data reception

•

In the slave reception mode, with ALS = “0” and immediately after

completion of slave address or general call address reception

•

In the slave reception mode, with ALS = “1” and immediately after

completion of address data reception

Part #	7207E
Description
Category	SWITCH
Availability	Out of Stock
Qty	0

7207E

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Technical Document