M54HC173
M74HC173
October 1992
QUAD D-TYPE REGISTER (3-STATE)
B1R
(Plastic Package)
ORDER CODES :
M54HC173F1R M74HC173M1R
M74HC173B1R M74HC173C1R
F1R
(CeramicPackage)
M1R
(Micro Package)
C1R
(Chip Carrier)
PIN CONNECTIONS (top view)
NC =
No Internal
Connection
DESCRIPTION
.HIGH SPEED
f
MAX
= 73 MHz (TYP.) at V
CC
=5V
.LOW POWER DISSIPATION
I
CC
=4µA (MAX.) at T
A
=25°C
.HIGH NOISE IMMUNITY
V
NIH
=V
NIL
=28%V
CC
(MIN.)
.OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
.SYMMETRICAL OUTPUT IMPEDANCE
|I
OH
|=I
OL
= 6 mA (MIN.)
.BALANCEDPROPAGATION DELAYS
t
PLH
=t
PHL
.WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V to 6 V
.PIN AND FUNCTION COMPATIBLE WITH
54/74LS 173
The M54/74HC173is ahigh speedCMOSQUADD-
TYPE REGISTER (3-STATE) fabricated in silicon
gate C
2
MOS technology.
It has the same high speed performance of LSTTL
combined with true CMOS low power consumption.
Thisdevice is composed ofa four-bit register includ-
ing D-typeflip-flops and3-state buffers. The fourflip-
flops are controlled by a common clock input
(CLOCK) and a common reset input (CLEAR). Sig-
nals applied to the data inputs (D
1
-D
4
) are stored at
the respective flip-flops on the positive going transi-
tion of the clock input, only when both clock control
inputs (G
1
and G
2
) are held low.
The reset feature is asynchronous and active high.
The stored data are provided on each output only
when both output control inputs (M and N) are held
low,otherwise the outputs go tothehigh-impedance
state.
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age.
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