ROSEMOUNT INC. 118JR

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Item Description: transducer surface resistance-435F to 1000F

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1 + $10.00000






Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Dual Bootstrapped 12 V MOSFET
Driver with Output Disable
ADP3118
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2005 Analog Devices, Inc. All rights reserved.
FEATURES
Optimized for low gate charge MOSFETs
All-in-one synchronous buck driver
Bootstrapped high-side drive
One PWM signal generates both drives
Anticross-conduction protection circuitry
Output disable control turns off both MOSFETs
to float output per Intel® VRM 10 specification
APPLICATIONS
Multiphase desktop CPU supplies
Single-supply synchronous buck converters
GENERAL DESCRIPTION
The ADP3118 is a dual high voltage MOSFET driver optimized
for driving two N-channel MOSFETs, which are the two switches
in a nonisolated synchronous buck power converter. Each of the
drivers is capable of driving a 3000 pF load with a 25 ns
propagation delay and a 25 ns transition time. One of the drivers
can be bootstrapped and is designed to handle the high voltage
slew rate associated with floating high-side gate drivers. The
ADP3118 includes overlapping drive protection to prevent
shoot-through current in the external MOSFETs.
The
OD
pin shuts off both the high-side and the low-side
MOSFETs to prevent rapid output capacitor discharge during
system shutdown.
The ADP3118 is specified over the commercial temperature
range of 0°C to 85°C and is available in 8-lead SOIC package.
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
2
3
OD
IN
ADP3118
VCC
BST
DRVH
SW
DRVL
PGND
DELAY
VCC
6
DELAY
CMP
CMP
1V
4
1
7
CONTROL
LOGIC
6
5
8
R
BST
R
G
C
BST1
D1
C
BST2
V
IN
12V
Q1
TO
INDUCTOR
Q2
05452-001
Figure 1.
Flex-Mode™ is Protected by U.S. Patent 6683441
ADP3118
Rev. 0 | Page 2 of 16
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Timing Characteristics..................................................................... 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ........................................................................ 9
Low-Side Driver............................................................................ 9
High-Side Driver .......................................................................... 9
Overlap Protection Circuit.......................................................... 9
Application Information................................................................ 10
Supply Capacitor Selection ....................................................... 10
Bootstrap Circuit........................................................................ 10
MOSFET Selection..................................................................... 10
High-Side (Control) MOSFETs................................................ 10
Low-Side (Synchronous) MOSFETs........................................ 11
PC Board Layout Considerations............................................. 11
Outline Dimensions ....................................................................... 13
Ordering Guide .......................................................................... 13
REVISION HISTORY
4/05Revision 0: Initial Version
ADP3118
Rev. 0 | Page 3 of 16
SPECIFICATIONS
1
V
CC
= 12 V, BST = 4 V to 26 V, T
A
= 0°C to 85°C, unless otherwise noted.
Table
1.
Parameter Symbol Conditions Min Typ Max Unit
PWM INPUT
Input Voltage High 2.0 V
Input Voltage Low 0.8 V
Input Current −1 +1 µA
Hysteresis 90 250 mV
OD INPUT
Input Voltage High 2.0 V
Input Voltage Low 0.8 V
Input Current −1 +1 µA
Hysteresis 90 250 mV
Propagation Delay Times
2
t
pdlOD
See Figure 3 20 35 ns
t
pdhOD
See Figure 3 40 55 ns
HIGH-SIDE DRIVER
Output Resistance, Sourcing Current BST − SW = 12 V 2.2 3.5
Output Resistance, Sinking Current BST − SW = 12 V 1.0 2.5
Output Resistance, Unbiased BST − SW = 0 V 10 kΩ
Transition Times
t
rDRVH
BST − SW = 12 V, C
LOAD
= 3 nF, see Figure 4 25 40 ns
t
fDRVH
BST − SW = 12 V, C
LOAD
= 3 nF, see Figure 4 20 30 ns
Propagation Delay Times
2
t
pdhDRVH
BST − SW = 12 V, C
LOAD
= 3 nF, see Figure 4 25 40 ns
t
pdlDRVH
BST − SW = 12 V, C
LOAD
= 3 nF, see Figure 4 25 35 ns
SW Pull-Down Resistance SW to PGND 10 kΩ
LOW-SIDE DRIVER
Output Resistance, Sourcing Current 2.0 3.2
Output Resistance, Sinking Current 1.0 2.5
Output Resistance, Unbiased VCC = PGND 10 kΩ
Transition Times
t
rDRVL
C
LOAD
= 3 nF, see Figure 4 20 35 ns
t
fDRVL
C
LOAD
= 3 nF, see Figure 4 16 30 ns
Propagation Delay Times
2
t
pdhDRVL
C
LOAD
= 3 nF, see Figure 4 12 35 ns
t
pdlDRVL
C
LOAD
= 3 nF, see Figure 4 30 45 ns
Timeout Delay SW = 5 V 110 190 ns
SW = PGND 95 150 ns
SUPPLY
Supply Voltage Range V
CC
4.15 13.2 V
Supply Current I
SYS
BST = 12 V, IN = 0 V 2 5 mA
UVLO Voltage VCC rising 1.5 3.0 V
Hysteresis 350 mV
1
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods.
2
For propagation delays, t
pdh
refers to the specified signal going high, and t
pdl
refers to it going low.
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