Electrical Characteristics
286 Datasheet
NOTES:
1. Determined with 2x MCH Buffer Strength Settings into a 50 Ω to 0.5xVCC_DDR test load.
2. Specified at the measurement point into a timing and voltage compliance test load as
shown in Transmitter compliance eye diagram of PCI Express* specification and measured
over any 250 consecutive TX Uls.
3. Specified at the measurement point over any 250 consecutive Uls. The test load shown in
Receiver compliance eye diagram of PCI Express* spec should be used as the RX device
when taking measurements.
4. Applies to pin to VCC or VSS leakage current for the DDR_A_DQ_63:0 and
DDR_B_DQ_63:0 signals.
5. Applies to pin to pin leakage current between DDR_A_DQS_7:0, DDR_A_DQSB_7:0,
DDR_B_DQS_7:0, and DDR_B_DQSB_7:0 signals.
6. Crossing voltage defined as instantaneous voltage when rising edge of BCLK0 equals
falling edge of BCLK1.
7. V
Havg
is the statistical average of the V
H
measured by the oscilloscope.
8. The crossing point must meet the absolute and relative crossing point specifications
simultaneously. Refer to the appropriate processor datasheet for further information.
§ §
PWROK, CL_PWROK, RSTIN#
V
IL
Input Low Voltage — — 0.3 V
V
IH
Input High Voltage 2.7 — — V
I
LEAK
Input Leakage Current — — ±1 mA
C
IN
Input Capacitance — — 6.0 pF
CL_RST#
V
IL
Input Low Voltage — — 0.13 V
V
IH
Input High Voltage 1.17 — — V
I
LEAK
Input Leakage Current — — ±20 μA
C
IN
Input Capacitance — — 5.0 pF
ICH_SYNCB
I
OL
Output Low Current (CMOS
Outputs)
——2.0mA
@V
OL_HI
max
I
OH
Output High Current (CMOS
Outputs)
-2.0 — — mA
@V
OH_HI
min
V
OL
Output Low Voltage (CMOS
Outputs)
——0.33V
V
OH
Output High Voltage (CMOS
Outputs)
2.97 — — V
EXP_SLR, EXP_EN
V
IL
Input Low Voltage -0.10 0
(0.63 x VTT) –
0.1
V
V
IH
Input High Voltage
(0.63 x
VTT)+0.1
VTT VTT +0.1 V
I
LEAK
Input Leakage Current — — 20 μA
V
OL
<
Vpad<
Vtt
C
IN
Input Capacitance 2 — 2.5 pF
Table 27. DC Characteristics
Symbol Parameter Min Nom Max Unit Notes
