Datasheet 283
Electrical Characteristics
11.4 Buffer Supply and DC Characteristics
11.4.1 I/O Buffer Supply Voltages
The I/O buffer supply voltage is measured at the MCH package pins. The tolerances
shown in Table 26 are inclusive of all noise from DC up to 20 MHz. In the lab, the
voltage rails should be measured with a bandwidth limited oscilloscope with a roll off of
3 dB/decade above 20 MHz under all operating conditions.
Table 26 indicates which supplies are connected directly to a voltage regulator or to a
filtered voltage rail. For voltages that are connected to a filter, they should me
measured at the input of the filter.
If the recommended platform decoupling guidelines cannot be met, the system
designer will have to make tradeoffs between the voltage regulator output DC tolerance
and the decoupling performance of the capacitor network to stay within the voltage
tolerances listed in Table 26.
NOTES:
1. These rails are filtered from other voltage rails on the platform and should be measured at
the input of the filter.
2. MCH supports both V
TT
=1.2 V nominal and V
TT
=1.1 V nominal depending on the
identified processor.
Table 26. I/O Buffer Supply Voltage
Symbol Parameter Min Nom Max Unit Notes
VCC_DDR DDR2 I/O Supply Voltage 1.7 1.8 1.9 V
VCC_DDR DDR3 I/O Supply Voltage 1.425 1.5 1.575 V
VCC_CKDDR DDR2 Clock Supply Voltage 1.7 1.8 1.9 V 1
VCC_CKDDR DDR3 Clock Supply Voltage 1.425 1.5 1.575 V 1
VCC_EXP PCI-Express* Supply Voltage 1.188 1.25 1.313 V
VCCA_EXP
PCI-Express* Analog Supply
Voltage
3.135 3.3 3.465 V 1
VTT_FSB
1.2 V System Bus Input Supply
Voltage
1.14 1.2 1.26 V
2
1.1 V System Bus Input Supply
Voltage
1.045 1.1 1.155 V
VCC MCH Core Supply Voltage 1.188 1.25 1.313 V
VCC_CL Controller Supply Voltage 1.188 1.25 1.313 V
VCC3_3 CMOS Supply Voltage 3.135 3.3 3.465 V
VCCA_HPLL,
VCCAPLL_EXP,
VCCA_MPLL
Various PLL Analog Supply
Voltages
1.188 1.25 1.313 V 1
