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Technical Document


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Electrical Characteristics
280 Datasheet
11.3 Signal Groups
The signal description includes the type of buffer used for the particular signal.
Type Description
PCI
Express*
PCI Express interface signals. These signals are compatible with PCI Express 2.0
Signaling Environment AC Specifications and are AC coupled. The buffers are not
3.3 V tolerant. Differential voltage spec = (|D+ – D-|) * 2 = 1.2Vmax. Single-ended
maximum = 1.25 V. Single-ended minimum = 0 V.
DMI
Direct Media Interface signals. These signals are compatible with PCI Express 1.0
Signaling Environment AC Specifications, but are DC coupled. The buffers are not
3.3 V tolerant. Differential voltage spec = (|D+ – D-|) * 2 = 1.2 Vmax. Single-
ended maximum = 1.25 V. Single-ended minimum = 0 V.
GTL+
Open Drain GTL+ interface signal. Refer to the GTL+ I/O Specification for complete
details.
HCSL
Host Clock Signal Level buffers. Current mode differential pair. Differential typical
swing = (|D+ – D-|) * 2 = 1.4 V. Single ended input tolerant from -0.35 V to 1.2 V.
Typical crossing voltage 0.35 V.
SSTL-1.8
Stub Series Termination Logic. These are 1.8 V output capable buffers. 1.8 V
tolerant.
SSTL-1.5
Stub Series Termination Logic. These are 1.5 V output capable buffers. 1.5 V
tolerant.
CMOS CMOS buffers
Analog
Analog reference or output. May be used as a threshold voltage or for buffer
compensation.
Datasheet 281
Electrical Characteristics
Table 25. Signal Groups
Signal Type Signals Notes
Host Interface Signal Groups
GTL+ Input/Outputs
FSB_ADSB, FSB_BNRB, FSB_DBSYB, FSB_DINVB_3:0,
FSB_DRDYB, FSB_AB_35:3, FSB_ADSTBB_1:0, FSB_DB_63:0,
FSB_DSTBPB_3:0, FSB_DSTBNB_3:0, FSB_HITB, FSB_HITMB,
FSB_REQB_4:0
GTL+ Common
Clock Outputs
FSB_BPRIB, FSB_BREQ0B, FSB_CPURSTB, FSB_DEFERB,
FSB_TRDYB, FSB_RSB_2:0
Analog Host I/F Ref
& Comp. Signals
FSB_RCOMP, FSB_SCOMP, FSB_SCOMPB, FSB_SWING,
FSB_DVREF, FSB_ACCVREF
GTL+ Input FSB_LOCKB, BSEL2:0
PCI Express* Graphics Interface Signal Groups
PCI Express* Input PCI Express* Interface: PEG_RXN_15:0, PEG_RXP_15:0
PCI Express* Output PCI Express* Interface: PEG_TXN_15:0, PEG_TXP_15:0
Analog PCI Express*
Compensation
Signals
EXP_COMPO, EXP_COMPI
Direct Media Interface Signal Groups
DMI Input DMI_RXP_3:0, DMI_RXN_3:0
DMI Output DMI_TXP_3:0, DMI_TXN_3:0
System Memory Interface Signal Groups
SSTL-1.8 / SSTL-1.5
Input/Output
DDR_A_DQ_63:0, DDR_A_DQS_7:0, DDR_A_DQSB_7:0
DDR_B_DQ_63:0, DDR_B_DQS_7:0, DDR_B_DQSB_7:0
DDR_A_CB_7:0, DDR_A_DQS_8, DDR_A_DQSB_8
DDR_B_CB_7:0, DDR_B_DQS_8, DDR_B_DQSB_8
1
SSTL-1.8 / SSTL-1.5
Output
DDR_A_CK_5:0, DDR_A_CKB_5:0, DDR_A_CSB_3:0,
DDR3_A_CSB_1, DDR_A_CKE_3:0, DDR_A_ODT_3:0,
DDR_A_MA_14:0, DDR3_A_MA_0, DDR_A_BS_2:0,
DDR_A_RASB, DDR_A_CASB, DDR_A_WEB, DDR3_A_WEB,
DDR_A_DM_7:0
DDR_B_CK_5:0, DDR_B_CKB_5:0, DDR_B_CSB_3:0,
DDR_B_CKE_3:0, DDR_B_ODT_3:0, DDR3_B_ODT_3,
DDR_B_MA_14:0, DDR_B_BS_2:0, DDR_B_RASB,
DDR_B_CASB, DDR_B_WEB, DDR_B_DM_7:0
DDR3_DRAMRST
CMOS Input DDR3_DRAM_PWROK
Reference and
Comp. Voltages
DDR_RCOMPXPD, DDR_RCOMPXPU, DDR_RCOMPYPD,
DDR_RCOMPYPU, DDR_VREF
Controller Link Signal Groups
CMOS I/O OD CL_DATA, CL_CLK
CMOS Input CL_RSTB, CL_PWROK
Analog Controller
Link Reference
Voltage
CL_VREF
Electrical Characteristics
282 Datasheet
NOTES:
1. CB_7:0, DQS[8], and DQSB[8] ECC signals are only for DDR2
Clocks
HCSL
HPL_CLKINP, HPL_CLKINN, EXP_CLKINP, EXP_CLKINN,
DPL_REFCLKINN, DPL_REFCLKINP
Reset, and Miscellaneous Signal Groups
CMOS Input EXP_SLR, PWROK, RSTINB
CMOS Output ICH_SYNCB
I/O Buffer Supply Voltages
System Bus Input
Supply Voltage
VTT_FSB
1.25 V PCI Express*
Supply Voltages
VCC_EXP
3.3 V PCI Express*
Analog Supply
Voltage
VCCA_EXP
1.8 V DDR2 / 1.5 V
DDR3 Supply
Voltage
VCC_DDR
1.8 V DDR2 / 1.5 V
DDR3 Clock Supply
Voltage
VCC_CKDDR
1.25 V MCH Core
Supply Voltage
VCC
1.25 V Controller
Supply Voltage
VCC_CL
3.3 V CMOS Supply
Voltage
VCC3_3
PLL Analog Supply
Voltages
VCCA_HPLL, VCCAPLL_EXP, VCCA_MPLL
Table 25. Signal Groups
Signal Type Signals Notes
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