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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Functional Description
274 Datasheet
10.4 Thermal Sensor
There are several registers that need to be configured to support the MCH thermal
sensor functionality and SMI# generation. Customers must enable the Catastrophic
Trip Point as protection for the MCH. If the Catastrophic Trip Point is crossed, then the
MCH will instantly turn off all clocks inside the device. Customers may optionally enable
the Hot Trip Point to generate SMI #. Customers will be required to then write their own
SMI# handler in BIOS that will speed up the MCH (or system) fan to cool the part.
10.4.1 PCI Device 0, Function 0
The SMICMD register requires that a bit be set to generate an SMI# when the Hot Trip
point is crossed. The ERRSTS register can be inspected for the SMI alert.
10.4.2 MCHBAR Thermal Sensor Registers
The Digital Thermometer Configuration Registers reside in the MCHBAR configuration
space.
Register Name
Register
Symbol
Register
Start
Register
End
Default
Value
Access
Error Status ERRSTS C8 C9 0000h RWC/S, RO
SMI Command SMICMD CC CD 0000h RO, RW
Register Name
Register
Symbol
Register
Start
Register
End
Default
Value
Access
Thermal Sensor Control 1 TSC1 CD8 CD8 00h
RW/L, RW,
RS/WC
Thermal Sensor Control 2 TSC2 CD9 CD9 00h RO, RW/L
Thermal Sensor Status TSS CDA CDA 00h RO
Thermal Sensor Temperature Trip
Point
TSTTP CDC CDF 00000000h RO, RW, RW/L
Thermal Calibration Offset TCO CE2 CE2 00h RW/L/K, RW/L
Hardware Throttle Control THERM1 CE4 CE4 00h
RW/L, RO,
RW/L/K
TCO Fuses THERM3 CE6 CE6 00h RO, RS/WC
Thermal Interrupt Status TIS CEA CEB 0000h RO, RWC
Thermal SMI Command TSMICMD CF1 CF1 00h RO, RW
Datasheet 275
Functional Description
10.5 Power Management
Power Management Feature List:
ACPI 1.0b support
ACPI S0, S1, S3 (Cold), S5, C0, C1, and C2 states
Enhanced power management state transitions for increasing time processor
spends in low power states
PCI Express Link States: L0, L0s, L2/L3 Ready, L3
10.6 Clocking
The MCH has a total of 3 PLLs providing many times that many internal clocks. The
PLLs are:
Host PLL – Generates the main core clocks in the host clock domain. Can also be
used to generate memory core clocks. Uses the Host clock (H_CLKIN) as a
reference.
Memory I/O PLL - Optionally generates low jitter clocks for memory I/O interface,
as opposed to from Host PLL. Uses the Host FSB differential clock (HPL_CLKINP/
HPL_CLKINN) as a reference. Low jitter clock source from memory I/O PLL is
required for DDR667 and higher frequencies.
PCI Express PLL – Generates all PCI Express related clocks, including the Direct
Media that connect to the ICH. This PLL uses the 100 MHz clock (EXP_CLKNP/
EXP2_CLKNP) as a reference.
CK505 is the clocking chip required for the platform.
Functional Description
276 Datasheet
§ §
Figure 10. System Clocking Diagram
PCI Down Device
CK
505
56
-
Pin SSOP
Intel® ICH9
OSC
32
.
768
kHz
PCI Express DIff Pair
SATA Diff Pair
PCI Slot
SIO LPC
TPM LPC
DMI
REF 14MHz
USB 48MHz
DOT 96MHz Diff
Pair
Memory
XDP
CPU
CPU Diff Pair
CPU Diff Pair
CPU Diff Pair
1
st
PCI Express
Dual
x16 PCI Express
2
nd
PCI Express
P
6
P
5
P
4
P
3
P
2
R
1
U
1
D
1
S
1
S
2
S
3
S
4
S
5
S
6
C
3
/
S
7
C
2
C
1
P
1
LAN (Nineveh)
PCI Express DIff Pair
PCI Express DIff Pair
PCI Express DIff Pair
PCI Express DIff Pair
PCI Express DIff Pair
PCI Express Slot
BCLK, ITPCLK, HCLK
SATACLK, ICHCLK,
MCHCLK, LANCLK,
PCIECLK
DOTCLK
USBCLK
PCICLK
REFCLK
C
1
-
C
3
S
1
-
S
7
D
1
U
1
P
1
-
P
6
R
1
Signal Name
Reference
Bearlake-X
MCH
NC
NC
PCI 33MHz
PCI 33MHz
PCI 33MHz
PCI 33MHz
PCI 33MHz
PCI 33MHz
PCI 33MHz
REF 14MHz
PCI Down Device
CK505
56- Pin SSOP
Inte
ICH9
OSC
32
.
768kHz
PCI Express
DIff Pair
SATA Diff Pair
PCI Slot
SIO LPC
TPM LPC
DMI
REF 14MHz
USB 48MHz
DOT 96MHz Diff Pair
Memory
XDP
Processor
Processor Diff Pair
Processor Diff Pair
Processor
Diff Pair
1
st
PCI Express
Dual
x16 PCI Express
2
nd
PCI Express
P6
P5
P4
P3
P2
R1
U1
D1
S1
S2
S3
S4
S5
S6
C3/S7
C2
C1
P1
LAN (Nineveh)
PCI Express DIff Pair
PCI Express
DIff Pair
PCI Express
DIff Pair
PCI Express
DIff Pair
PCI Express DIff Pair
PCI Express Slot
BCLK, ITPCLK, HCLK
SATACLK, ICHCLK,
MCHCLK, LANCLK,
PCIECLK
DOTCLK
USBCLK
PCICLK
REFCLK
C1- C3
S1-S7
D1
U1
P1- P6
R1
Signal Name Ref.
MCH
NC
NC
PCI 33MHz
PCI 33MHz
PCI 33MHz
PCI 33MHz
PCI 33MHz
PCI 33MHz
PCI 33MHz
REF 14MHz
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