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Technical Document


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Datasheet 271
Functional Description
33 (31) X X X X X
34 (CB3) X
35 (CB4) X
36 (32) XXX
37 (33) X X X
38 (34) X X X
39 (35) X X X
40 (36) X X X
41 (37) XXX
42 (38) X X X
43 (39) X X X
44 (40) X X X
45 (41) X X X
46 (42)XXX
47 (43) X X X
48 (44) X X X
49 (45) X X X
50 (46) X X X
51 (47) X X X
52 (48) X X X
53 (49) X X X
54 (50) X X X
55 (51) X X X
56 (52) X X X
57 (53) X X X
58 (54) X X X
59 (55) X X X
60 (56) X X X X X
61 (57) XXXX X
62 (CB6) X
63 (CB1) X
CB0 (58) X X X
CB1 (59) X X X
CB2 (60) X X X
CB3 (61) X X X
CB4 (62) X X X X X
Table 22. Syndrome Bit Values
Syndrome Bit >
Data Bit
76543210
Functional Description
272 Datasheet
Every data bit appears in either exactly 3 or exactly 5 check bit and syndrome bit
equations. Every check bit appears en exactly 1 syndrome bit equation. This leads to
six cases.
1. If the data comes back exactly as it was written, then the calculated check byte will
match the stored check byte, and the syndrome will be all 0s.
2. If exactly one check bit is flipped between the time it is written and the time it is
read back, then the syndrome will contain exactly one 1. Since the check byte is
not returned to the requesting agent, no action is necessary.
3. If exactly one data bit is flipped between the time it is written and the time it is
read back, then the syndrome will contain either exactly three 1s or exactly five 1s.
The syndrome can then be decoded as a pointer to the bit that flipped using the
same check byte generation table in reverse. If the syndrome contains 1s that
match the locations of all three or all five Xs in a given row, then that is the bit
which should be flipped before the QWord is returned to the requesting agent.
4. If exactly two bits flipped, there will be a nonzero even number of 1s in the
syndrome. It cannot be determined which bits flipped based on that syndrome, but
a multi-bit error will be recorded along with the address at which the error
occurred. In addition, bits 0 and 31 of each DWord are forced to 0 in the returned
data in case this read was a TLB fetch. This ensures that the table entry is invalid,
such that additional data corruption can be avoided.
5. If an even number of bits greater than two flipped, there will be an even number of
1s in the syndrome, but that even number could be zero, such that detection of this
scenario is not ensured. If the syndrome contains a nonzero number of 1s, it
cannot be distinguished from scenario 4 above.
6. It is possible for an odd number of bits greater than one to flip between the time
the data is written and the time it is read back. This scenario will always be
detected, but the resulting syndrome could appear to be a multi-bit error treated
similarly to scenario 4, or it could be misinterpreted as a single bit error
indistinguishable from scenario 2. The data cannot be corrected, though if it
appears to be a single-bit error, the algorithm will flip the bit that corresponds to
the syndrome generated, thus an additional bit may be corrupted.
Fortunately, soft error rates are low enough that it is extremely unlikely that there
would be more than one soft error in the same QWord, so scenarios 5 and 6 are very
rare.
CB5 (63) X X X X X
CB6 (CB7) X
CB7 (CB0) X
Table 22. Syndrome Bit Values
Syndrome Bit >
Data Bit
76543210
Datasheet 273
Functional Description
10.3 PCI Express*
See Section 1.2 for a list of PCI Express features, and the PCI Express specification for
further details.
This MCH is part of a PCI Express root complex. This means it connects a host
processor/memory subsystem to a PCI Express hierarchy. The control registers for this
functionality are located in Device 1 and Device 6 configuration space and three Root
Complex Register Blocks (RCRBs). The DMI RCRB contains registers for control of the
Intel ICH9 attach ports.
10.3.1 PCI Express* Architecture
The PCI Express architecture is specified in layers. Compatibility with the PCI
addressing model (a load-store architecture with a flat address space) is maintained to
ensure that all existing applications and drivers operate unchanged. The PCI Express
configuration uses standard mechanisms as defined in the PCI Plug-and-Play
specification. The initial speed of 2.5 GHz results in 5 Gb/s each direction, which
provides a 500 MB/s communications channel in each direction (1000 MB/s total).
10.3.1.1 Transaction Layer
The upper layer of the PCI Express architecture is the Transaction Layer. The
Transaction Layer’s primary responsibility is the assembly and disassembly of
Transaction Layer Packets (TLPs). TLPs are used to communicate transactions, such as
read and write, as well as certain types of events. The Transaction Layer also manages
flow control of TLPs.
10.3.1.2 Data Link Layer
The middle layer in the PCI Express stack, the Data Link Layer, serves as an
intermediate stage between the Transaction Layer and the Physical Layer.
Responsibilities of Data Link Layer include link management, error detection, and error
correction.
10.3.1.3 Physical Layer
The Physical Layer includes all circuitry for interface operation, including driver and
input buffers, parallel-to-serial and serial-to-parallel conversion, PLL(s), and impedance
matching circuitry.
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