Functional Description

268 Datasheet

10.2.1.2.2 Dual Channel Asymmetric Mode with Intel

Flex Memory Mode Enabled

In this addressing mode the lowest DRAM memory is mapped to dual channel operation

and the top most DRAM memory is mapped to single channel operation. In this mode

the system can run at one zone of dual channel mode and one zone of single channel

mode simultaneously across the whole memory array.

This mode is used when Intel

Flex Memory Mode is enabled and both Channel A and

Channel B DIMMs are populated in any order with the total amount of memory in each

channel being different.

Table 19 is a sample dual channel asymmetric memory configuration showing the rank

organization with Intel

Flex Memory Mode Enabled.

10.2.1.2.3 Dual Channel Asymmetric Mode with Intel

Flex Memory Mode Disabled

In this addressing mode addresses start in channel 0 and stay there until the end of the

highest rank in channel 0, and then addresses continue from the bottom of channel 1

to the top.

This mode is used when Intel

Flex Memory Mode is disabled and both Channel A and

Channel B DIMMs are populated in any order with the total amount of memory in each

channel being different.

Table 20 is a sample dual channel asymmetric memory configuration showing the rank

organization with Intel

Flex Memory Mode Disabled:

Table 19. Sample System Memory Dual Channel Asymmetric Organization Mode with

Intel

Flex Memory Mode Enabled

Rank

Channel 0

population

Cumulative top

address in

Channel 0

Channel 1

population

Cumulative top

address in

Channel 1

Rank 3 0 MB 2048 MB 0 MB 2304 MB

Rank 2 0 MB 2048 MB 256 MB 2304 MB

Rank 1 512 MB 2048 MB 512 MB 2048 MB

Rank 0 512 MB 1024 MB 512 MB 1024 MB

Table 20. Sample System Memory Dual Channel Asymmetric Organization Mode with

Intel

Flex Memory Mode Disabled

Rank

Channel 0

population

Cumulative top

address in

Channel 0

Channel 1

population

Cumulative top

address in

Channel 1

Rank 3 0 MB 1280 MB 0 MB 2304 MB

Rank 2 256 MB 1280 MB 0 MB 2304 MB

Rank 1 512 MB 1024 MB 512 MB 2304 MB

Rank 0 512 MB 512 MB 512 MB 1792 MB

Datasheet 269

Functional Description

10.2.2 System Memory Technology Supported

The MCH supports the following DDR2 and DDR3 Data Transfer Rates, DIMM Modules,

and DRAM Device Technologies:

• DDR2 Data Transfer Rates: 667 (PC2-5300) and 800 (PC2-6400)

• DDR3 Data Transfer Rates: 800 (PC3-6400), 1066 (PC3-8500), and 1333 (PC3-

10600)

•DDR2 DIMM Modules:

— Raw Card C - Single Sided x16 un-buffered non-ECC

— Raw Card D - Single Sided x8 un-buffered non-ECC

— Raw Card E - Double Sided x8 un-buffered non-ECC

— Raw Card F - Single Sided x8 un-buffered ECC

— Raw Card G - Double Sided x8 un-buffered ECC

•DDR3 DIMM Modules:

— Raw Card A - Single Sided x8 un-buffered non-ECC

— Raw Card B - Double Sided x8 un-buffered non-ECC

— Raw Card C - Single Sided x16 un-buffered non-ECC

— Raw Card F - Double Sided x16 un-buffered non-ECC

• DDR2 and DDR3 DRAM Device Technology: 512-Mb and 1-Gb

Table 21. Supported DIMM Module Configurations

Memory

Type

Raw

Card

Version

DIMM

Capacity

DRAM

Device

Technology

DRAM

Organization

# of

DRAM

Devices

# of

Physical

Device

Ranks

# of

Row/

Col

Address

Bits

# of

Banks

Inside

DRAM

Page

Size

DDR2

667 and

800

256MB 512Mb 32M X 16 4 1 13/10 4 8K

512MB 1Gb 64M X 16 4 1 13/10 8 8K

512MB 512Mb 64M X 8 8 1 14/10 4 8K

1GB 1Gb 128M X 8 8 1 14/10 8 8K

1GB 512Mb 64M X 8 16 2 14/10 4 8K

2GB 1Gb 128M X 8 16 2 14/10 8 8K

512MB 512Mb 64M X 8 9 1 14/10 4 8K

1GB 1Gb 128M X 8 9 1 14/10 8 8K

1GB 512Mb 64M X 8 18 2 14/10 4 8K

2GB 1Gb 128M X 8 18 2 14/10 8 8K

DDR3

800 and

1066

512MB 512Mb 64M X 8 8 1 13/10 8 8K

1GB 1Gb 128M X 8 8 1 14/10 8 8K

1GB 512Mb 64M X 8 16 2 13/10 8 8K

2GB 1Gb 128M X 8 16 2 14/10 8 8K

256MB 512Mb 32M X 16 4 1 12/10 8 8K

512MB 1Gb 64M X 16 4 1 13/10 8 8K

512MB 512Mb 32M X 16 8 2 12/10 8 8K

1GB 1Gb 64M X 16 8 2 13/10 8 8K

Functional Description

270 Datasheet

10.2.3 Error Checking and Correction

Table 22 is used to calculate the syndrome. Numbers in parentheses indicate the data

content of that bit position. For example, bit position 36 holds the data originally in

data bit 32.

Table 22. Syndrome Bit Values

Syndrome Bit >

Data Bit

76543210

0XX X

1XX X

2XX X

3XX X

4XX X

5XX X

6XX X

7XXX

8X X X

9X X X

10 X X X

11 X X X

12 X X X

13 X X X

14 X X X

15 X X X

16 X X X

17 X X X

18 XXX

19 X X X

20 X X X

21 X X X

22 X X X

23 X X X

24 XXXXX

25 X X X X X

26 (CB2) X

27 (CB5) X

28 (26) X X X

29 (27) X X X

30 (28) X X X

31 (29) X X X

32 (30) X X X X X

Part #	31761
Description
Category	RELAY
Availability	In Stock
Qty	1

31761

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