Datasheet 267
Functional Description
10.2 System Memory Controller
The system memory controller supports both DDR2 and DDR3 protocols with two
independent 64 bit wide channels each accessing one or two DIMMs. It supports a
maximum of two un-buffered ECC or non-ECC DDR2 DIMMs or two un-buffered non-
ECC DDR3 DIMMs per channel thus allowing up to four device ranks per channel.
10.2.1 System Memory Organization Modes
The system memory controller supports two memory organization modes, Single
Channel and Dual Channel.
10.2.1.1 Single Channel Mode
In this mode, all memory cycles are directed to a single channel.
Single channel mode is used when either Channel A or Channel B DIMMs are populated
in any order, but not both.
10.2.1.2 Dual Channel Modes
10.2.1.2.1 Dual Channel Symmetric Mode
This mode provides maximum performance on real applications. Addresses are ping-
ponged between the channels after each cache line (64 byte boundary). If there are
two requests, and the second request is to an address on the opposite channel from the
first, that request can be sent before data from the first request has returned. If two
consecutive cache lines are requested, both may be retrieved simultaneously, since
they are guaranteed to be on opposite channels.
Dual channel symmetric mode is used when both Channel A and Channel B DIMMs are
populated in any order with the total amount of memory in each channel being the
same, but the DRAM device technology and width may vary from one channel to the
other.
Table 18 is a sample dual channel symmetric memory configuration showing the rank
organization.
Table 18. Sample System Memory Dual Channel Symmetric Organization Mode
Rank
Channel 0
Population
Cumulative Top
Address in
Channel 0
Channel 1
Population
Cumulative Top
Address in
Channel 1
Rank 3 0 MB 2560 MB 0 MB 2560 MB
Rank 2 256 MB 2560 MB 256 MB 2560 MB
Rank 1 512 MB 2048 MB 512 MB 2048 MB
Rank 0 512 MB 1024 MB 512 MB 1024 MB
