Datasheet 247

Host-Secondary PCI Express* Bridge Registers (D6:F0)

8.44 RCTL—Root Control

B/D/F/Type: 0/6/0/PCI

Address Offset: BC–BDh

Default Value: 0000h

Access: RO, RW

Size: 16 bits

This register allows control of PCI Express Root Complex specific parameters. The

system error control bits in this register determine if corresponding SERRs are

generated when our device detects an error (reported in this device's Device Status

controlled by these bits takes precedence over the SERR Enable in the PCI Command

Bit Access

Default

Value

Description

15:4 RO 000h Reserved

3RW0b

PME Interrupt Enable (PMEIE):

0 = No interrupts are generated as a result of receiving PME messages.

1 = Enables interrupt generation upon receipt of a PME message as reflected in

the PME Status bit of the Root Status Register. A PME interrupt is also

generated if the PME Status bit of the Root Status Register is set when this

bit is set from a cleared state.

2RW0b

System Error on Fatal Error Enable (SEFEE): Controls the Root Complex's

response to fatal errors.

0 = No SERR generated on receipt of fatal error.

1 = Indicates that an SERR should be generated if a fatal error is reported by

any of the devices in the hierarchy associated with this Root Port, or by the

Root Port itself.

1RW0b

System Error on Non-Fatal Uncorrectable Error Enable (SENFUEE):

Controls the Root Complex's response to non-fatal errors.

0 = No SERR generated on receipt of non-fatal error.

1 = Indicates that an SERR should be generated if a non-fatal error is reported

by any of the devices in the hierarchy associated with this Root Port, or by

the Root Port itself.

0RW0b

System Error on Correctable Error Enable (SECEE): Controls the Root

Complex's response to correctable errors.

0 = No SERR generated on receipt of correctable error.

1 = Indicates that an SERR should be generated if a correctable error is reported

by any of the devices in the hierarchy associated with this Root Port, or by

the Root Port itself.

Host-Secondary PCI Express* Bridge Registers (D6:F0)

248 Datasheet

8.45 RSTS—Root Status

B/D/F/Type: 0/6/0/PCI

Address Offset: C0–C3h

Default Value: 00000000h

Access: RO, RWC

Size: 32 bits

This register provides information about PCI Express Root Complex specific

parameters.

8.46 PELC—PCI Express Legacy Control

B/D/F/Type: 0/6/0/PCI

Address Offset: EC–EFh

Default Value: 00000000h

Access: RO, RW

Size: 32 bits

This register controls functionality that is needed by Legacy (non-PCI Express aware)

OSs during run time.

Bit Access

Default

Value

Description

31:18 RO 0000h Reserved

17 RO 0b

PME Pending (PMEP): Indicates that another PME is pending when the PME

Status bit is set. When the PME Status bit is cleared by software; the PME is

delivered by hardware by setting the PME Status bit again and updating the

Requestor ID appropriately. The PME pending bit is cleared by hardware if no

more PMEs are pending.

16 RWC 0b

PME Status (PMES): Indicates that PME was asserted by the requestor ID

indicated in the PME Requestor ID field. Subsequent PMEs are kept pending until

the status register is cleared by writing a 1 to this field.

15:0 RO 0000h

PME Requestor ID (PMERID): Indicates the PCI requestor ID of the last PME

requestor.

Bit Access

Default

Value

Description

31:3 RO

0000000

Reserved

2RW0b

PME GPE Enable (PMEGPE):

0 = Do not generate GPE PME message when PME is received.

1 = Generate a GPE PME message when PME is received (Assert_PMEGPE and

Deassert_PMEGPE messages on DMI). This enables the MCH to support

PMEs on the PCI Express port under legacy OSs.

1 RO 0b Reserved

0RW0b

General Message GPE Enable (GENGPE):

0 = Do not forward received GPE assert/de-assert messages.

1 = Forward received GPE assert/de-assert messages. These general GPE

message can be received via the PCI Express port from an external Intel

device and will be subsequently forwarded to the ICH (via Assert_GPE and

Deassert_GPE messages on DMI).

Datasheet 249

Host-Secondary PCI Express* Bridge Registers (D6:F0)

8.47 VCECH—Virtual Channel Enhanced Capability

Header

B/D/F/Type: 0/6/0/MMR

Address Offset: 100–103h

Default Value: 14010002h

Access: RO

Size: 32 bits

This register indicates PCI Express device Virtual Channel capabilities. Extended

capability structures for PCI Express devices are located in PCI Express extended

configuration space and have different field definitions than standard PCI capability

structures.

8.48 PVCCAP1—Port VC Capability Register 1

B/D/F/Type: 0/6/0/MMR

Address Offset: 104–107h

Default Value: 00000000h

Access: RO

Size: 32 bits

This register describes the configuration of PCI Express Virtual Channels associated

with this port.

Bit Access

Default

Value

Description

31:20 RO 140h

Pointer to Next Capability (PNC): The Link Declaration Capability is the next

in the PCI Express extended capabilities list.

19:16 RO 1h

PCI Express Virtual Channel Capability Version (PCIEVCCV): Hardwired to

1 to indicate compliances with the 1.1 version of the PCI Express specification.

Note: This version does not change for 2.0 compliance.

15:0 RO 0002h

Extended Capability ID (ECID): Value of 0002h identifies this linked list item

(capability structure) as being for PCI Express Virtual Channel registers.

Bit Access

Default

Value

Description

31:7 RO 00000h Reserved

6:4 RO 000b

Low Priority Extended VC Count (LPEVCC): This field indicates the number

of (extended) Virtual Channels in addition to the default VC belonging to the low-

priority VC (LPVC) group that has the lowest priority with respect to other VC

resources in a strict-priority VC Arbitration.

The value of 0 in this field implies strict VC arbitration.

3 RO 0b Reserved

2:0 RO 000b

Extended VC Count (EVCC): This field indicates the number of (extended)

Virtual Channels in addition to the default VC supported by the device.

Part #	31761
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Category	RELAY
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31761

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