Host-Secondary PCI Express* Bridge Registers (D6:F0)
242 Datasheet
8.40 LSTS—Link Status
B/D/F/Type: 0/6/0/PCI
Address Offset: B2–B3h
Default Value: 1000h
Access: RWC, RO
Size: 16 bits
This register indicates PCI Express link status.
Bit Access
Default
Value
Description
15 RWC 0b
Link Autonomous Bandwidth Status (LABWS): This bit is set to 1b by
hardware to indicate that hardware has autonomously changed link speed or
width, without the port transitioning through DL_Down status, for reasons other
than to attempt to correct unreliable link operation.
This bit must be set if the Physical Layer reports a speed or width change was
initiated by the downstream component that was indicated as an autonomous
change.
14 RWC 0b
Link Bandwidth Management Status (LBWMS): This bit is set to 1b by
hardware to indicate that either of the following has occurred without the port
transitioning through DL_Down status:
A link retraining initiated by a write of 1b to the Retrain Link bit has completed.
NOTE: This bit is Set following any write of 1b to the Retrain Link bit, including
when the Link is in the process of retraining for some other reason.
Hardware has autonomously changed link speed or width to attempt to correct
unreliable link operation, either through an LTSSM timeout or a higher level
process
This bit must be set if the Physical Layer reports a speed or width change was
initiated by the downstream component that was not indicated as an
autonomous change.
13 RO 0b
Data Link Layer Link Active (Optional) (DLLLA): This bit indicates the
status of the Data Link Control and Management State Machine. It returns a 1b
to indicate the DL_Active state, 0b otherwise.
This bit must be implemented if the corresponding Data Link Layer Active
Capability bit is implemented. Otherwise, this bit must be hardwired to 0b.
12 RO 1b
Slot Clock Configuration (SCC):
0 = The device uses an independent clock irrespective of the presence of a
reference on the connector.
1 = The device uses the same physical reference clock that the platform
provides on the connector.
11 RO 0b
Link Training (LTRN): This bit indicates that the Physical Layer LTSSM is in the
Configuration or Recovery state, or that 1b was written to the Retrain Link bit
but Link training has not yet begun. Hardware clears this bit when the LTSSM
exits the Configuration/Recovery state once Link training is complete.
10 RO 0b
Undefined: The value read from this bit is undefined. In previous versions of
this specification, this bit was used to indicate a Link Training Error. System
software must ignore the value read from this bit. System software is permitted
to write any value to this bit.
