Datasheet 237
Host-Secondary PCI Express* Bridge Registers (D6:F0)
8.37 DSTS—Device Status
B/D/F/Type: 0/6/0/PCI
Address Offset: AA–ABh
Default Value: 0000h
Access: RO, RWC
Size: 16 bits
This register reflects status corresponding to controls in the Device Control register.
The error reporting bits are in reference to errors detected by this device, not errors
messages received across the link.
Bit Access
Default
Value
Description
15:6 RO 000h Reserved
5RO0b
Transactions Pending (TP):
0 = All pending transactions (including completions for any outstanding non-
posted requests on any used virtual channel) have been completed.
1 = Indicates that the device has transaction(s) pending (including completions
for any outstanding non-posted requests for all used Traffic Classes).
4 RO 0b Reserved
3RWC0b
Unsupported Request Detected (URD): When set, this bit indicates that the
Device received an Unsupported Request. Errors are logged in this register
regardless of whether error reporting is enabled or not in the Device Control
Register.
Additionally, the Non-Fatal Error Detected bit or the Fatal Error Detected bit is
set according to the setting of the Unsupported Request Error Severity bit. In
production systems setting the Fatal Error Detected bit is not an option as
support for AER will not be reported.
2RWC0b
Fatal Error Detected (FED): When set, this bit indicates that fatal error(s)
were detected. Errors are logged in this register regardless of whether error
reporting is enabled or not in the Device Control register. When Advanced Error
Handling is enabled, errors are logged in this register regardless of the settings
of the uncorrectable error mask register.
1RWC0b
Non-Fatal Error Detected (NFED): When set, this bit indicates that non-fatal
error(s) were detected. Errors are logged in this register regardless of whether
error reporting is enabled or not in the Device Control register.
When Advanced Error Handling is enabled, errors are logged in this register
regardless of the settings of the uncorrectable error mask register.
0RWC0b
Correctable Error Detected (CED): When set, this bit indicates that
correctable error(s) were detected. Errors are logged in this register regardless
of whether error reporting is enabled or not in the Device Control register.
When Advanced Error Handling is enabled, errors are logged in this register
regardless of the settings of the correctable error mask register.
