Host-Secondary PCI Express* Bridge Registers (D6:F0)
212 Datasheet
1E–1Fh SSTS1 Secondary Status 0000h RO, RWC
20–21h MBASE1 Memory Base Address FFF0h RW, RO
22–23h MLIMIT1 Memory Limit Address 0000h RW, RO
24–25h PMBASE1 Prefetchable Memory Base Address FFF1h RW, RO
26–27h PMLIMIT1 Prefetchable Memory Limit Address 0001h RO, RW
28–2Bh PMBASEU1 Prefetchable Memory Base Address Upper 00000000h RW
2C–2Fh PMLIMITU1 Prefetchable Memory Limit Address Upper 00000000h RW
34h CAPPTR1 Capabilities Pointer 88h RO
3Ch INTRLINE1 Interrupt Line 00h RW
3Dh INTRPIN1 Interrupt Pin 01h RO
3E–3Fh BCTRL1 Bridge Control 0000h RO, RW
80–83h PM_CAPID1 Power Management Capabilities C8039001h RO
84–87h PM_CS1 Power Management Control/Status 00000008h
RO, RW,
RW/P
88–8Bh SS_CAPID Subsystem ID and Vendor ID Capabilities 0000800Dh RO
8C–8Fh SS Subsystem ID and Subsystem Vendor ID 00008086h RWO
90–91h MSI_CAPID Message Signaled Interrupts Capability ID A005h RO
92–93h MC Message Control 0000h RW, RO
94–97h MA Message Address 00000000h RO, RW
98–99h MD Message Data 0000h RW
A0–A1h PE_CAPL PCI Express Capability List 0010h RO
A2–A3h PE_CAP PCI Express Capabilities 0142h RO, RWO
A4–A7h DCAP Device Capabilities 00008000h RO
A8–A9h DCTL Device Control 0000h RW, RO
AA–ABh DSTS Device Status 0000h RO, RWC
AC–AFh LCAP Link Capabilities 03214D02h RO, RWO
B0–B1h LCTL Link Control 0000h
RO, RW,
RW/SC
B2–hB3 LSTS Link Status 1000h RWC, RO
B4–B7h SLOTCAP Slot Capabilities 00040000h RWO, RO
B8–B9h SLOTCTL Slot Control 0000h RO, RW
BA–BBh SLOTSTS Slot Status 0000h RO, RWC
BC–BDh RCTL Root Control 0000h RO, RW
C0–C3h RSTS Root Status 00000000h RO, RWC
EC–EFh PELC PCI Express Legacy Control 00000000h RO, RW
100–103h VCECH
Virtual Channel Enhanced Capability
Header
14010002h RO
Table 15. Host-Secondary PCI Express* Bridge Register Address Map (D6:F0) (Sheet 2
of 3)
Address
Offset
Register
Symbol
Register Name
Default
Value
Access
