Intel Manageability Engine Subsystem PCI (D3:F0,F3)
202 Datasheet
7.2 KT IO/ Memory Mapped Device Specific Registers
[D3:F3]
7.2.1 KTRxBR—KT Receive Buffer
B/D/F/Type: 0/3/3/KT MM/IO
Address Offset: 0h
Default Value: 00h
Access: RO/V
Size: 8 bits
This implements the KT Receiver Data register. Host access to this address, depends on
the state of the DLAB bit {KTLCR[7]). It must be 0 to access the KTRxBR.
RxBR:
Host reads this register when FW provides it the receive data in non-FIFO mode. In
FIFO mode, host reads to this register translate into a read from ME memory (RBR
FIFO).
Note: Reset: Host System Reset or D3->D0 transition.
Table 14. KT IO/Memory Mapped Register Address Map
Address
Offset
Register
Symbol
Register Name
Default
Value
Access
0h KTRxBR KT Receive Buffer 00h RO/V
0h KTTHR KT Transmit Holding 00h WO
0h KTDLLR KT Divisor Latch LSB 00h RW/V
1h KTIER KT Interrupt Enable 00h RW/V, RO/V
1h KTDLMR KT Divisor Latch MSB 00h RW/V
2h KTIIR KT Interrupt Identification 01h RO
2h KTFCR KT FIFO Control 00h WO
3h KTLCR KT Line Control 03h RW
4h KTMCR KT Modem Control 00h RO, RW
5h KTLSR KT Line Status 00h RO, RO/CR
6h KTMSR KT Modem Status 00h RO, RO/CR
7h KTSCR KT Scratch 00h RW
Bit Access
Default
Value
Description
7:0 RO/V 00h
Receiver Buffer Register (RBR): Implements the Data register of the Serial
Interface. If the Host does a read, it reads from the Receive Data Buffer.
