Datasheet 199
Intel Manageability Engine Subsystem PCI (D3:F0,F3)
7.1.19 MID—Message Signaled Interrupt Identifiers
B/D/F/Type: 0/3/0/PCI
Address Offset: 8C–8Dh
Default Value: 0005h
Access: RO
Size: 16 bits
7.1.20 MC—Message Signaled Interrupt Message Control
B/D/F/Type: 0/3/0/PCI
Address Offset: 8E–8Fh
Default Value: 0080h
Access: RO, RW
Size: 16 bits
3RO1b
No_Soft_Reset (NSR): This bit indicates that when the HECI host controller is
transitioning from D3hot to D0 due to power state command, it does not perform
an internal reset.
2 RO 0b Reserved
1:0 RW 00b
Power State (PS): This field is used both to determine the current power state
of the HECI host controller and to set a new power state. The values are:
00 = D0 state
11 = D3HOT state
The D1 and D2 states are not supported for this HECI host controller. When in
the D3HOT state, the HBA’s configuration space is available, but the register
memory spaces are not. Additionally, interrupts are blocked.
Bit Access
Default
Value
Description
Bit Access
Default
Value
Description
15:8 RO 00h
Next Pointer (NEXT): Indicates the next item in the list. This can be other
capability pointers (such as PCI-X or PCI-Express) or it can be the last item in
the list.
7:0 RO 05h Capability ID (CID): Capabilities ID indicates MSI.
Bit Access
Default
Value
Description
15:8 RO 00h Reserved
7RO1b
64 Bit Address Capable (C64): Specifies whether capable of generating 64-bit
messages.
6:4 RO 000b Multiple Message Enable (MME): Not implemented, hardwired to 0.
3:1 RO 000b Multiple Message Capable (MMC): Not implemented, hardwired to 0.
0RW0b
MSI Enable (MSIE): If set, MSI is enabled and traditional interrupt pins are not
used to generate interrupts.
