Intel Manageability Engine Subsystem PCI (D3:F0,F3)
198 Datasheet
7.1.17 PC—PCI Power Management Capabilities
B/D/F/Type: 0/3/0/PCI
Address Offset: 52–53h
Default Value: C803h
Access: RO
Size: 16 bits
7.1.18 PMCS—PCI Power Management Control And Status
B/D/F/Type: 0/3/0/PCI
Address Offset: 54–55h
Default Value: 0008h
Access: RWC, RO, RW
Size: 16 bits
Bit Access
Default
Value
Description
15:11 RO 11001b
PME_Support (PSUP): Indicates the states that can generate PME#.
HECI can assert PME# from any D-state except D1 or D2 which are not
supported by HECI.
10 RO 0b D2_Support (D2S): The D2 state is not supported for the HECI host controller.
9RO0bD1_Support (D1S): The D1 state is not supported for the HECI host controller.
8:6 RO 000b
Aux_Current (AUXC): Reports the maximum Suspend well current required
when in the D3COLD state.
5RO0b
Device Specific Initialization (DSI): Indicates whether device-specific
initialization is required.
4 RO 0b Reserved
3RO0bPME Clock (PMEC): Indicates that PCI clock is not required to generate PME#.
2:0 RO 011b
Version (VS): Indicates support for Revision 1.2 of the PCI Power Management
Specification.
Bit Access
Default
Value
Description
15 RWC 0b
PME Status (PMES): The PME Status bit in HECI space can be set to '1' by ME
FW performing a write into AUX register to set PMES.
This bit is cleared by host processor writing a '1' to it.
ME cannot clear this bit.
Host processor writes with value '0' have no effect on this bit.
This bit is reset to '0' by MRST#
14:9 RO 000000b Reserved
8RW0b
PME Enable (PMEE): This bit is read/write, under control of host SW. It does
not directly have an effect on PME events. However, this bit is shadowed into
AUX space so ME FW can monitor it. The ME FW is responsible for ensuring that
FW does not cause the PME-S bit to transition to '1' while the PMEE bit is '0',
indicating that host SW had disabled PME.
This bit is reset to '0' by MRST#
7:4 RO 0000b Reserved
