Freelance Electronics Components Distributor
Closed Dec 25th-26th
800-300-1968
We Stock Hard to Find Parts

31761

Part # 31761
Description
Category RELAY
Availability In Stock
Qty 1
Qty Price
1 + $8.31832
Manufacturer Available Qty
ARROW HART
  • Shipping Freelance Stock: 1
    Ships Immediately



Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Datasheet 193
Intel Manageability Engine Subsystem PCI (D3:F0,F3)
7.1.3 STS—Device Status
B/D/F/Type: 0/3/0/PCI
Address Offset: 6–7h
Default Value: 0010h
Access: RO
Size: 16 bits
7.1.4 RID—Revision ID
B/D/F/Type: 0/3/0/PCI
Address Offset: 8h
Default Value: see table below
Access: RO
Size: 8 bits
7.1.5 CC—Class Code
B/D/F/Type: 0/3/0/PCI
Address Offset: 9–Bh
Default Value: 0C8001h
Access: RO
Size: 24 bits
Bit Access
Default
Value
Description
15:5 RO 0h Reserved
4RO1b
Capabilities List (CL): Indicates the presence of a capabilities list, hardwired to
1.
3RO0b
Interrupt Status (IS): Indicates the interrupt status of the device
1 = Asserted
2:0 RO 000b Reserved
Bit Access
Default
Value
Description
7:0 RO
See
Description
Revision ID (RID): This field indicates stepping of the HECI host controller.
Refer to the Intel
®
X38 Express Chipset Specification Update for the value of
this register.
Bit Access
Default
Value
Description
23:16 RO 0ch
Base Class Code (BCC): Indicates the base class code of the HECI host
controller device.
15:8 RO 80h
Sub Class Code (SCC): Indicates the sub class code of the HECI host controller
device.
7:0 RO 01h
Programming Interface (PI): Indicates the programming interface of the
HECI host controller device.
Intel Manageability Engine Subsystem PCI (D3:F0,F3)
194 Datasheet
7.1.6 CLS—Cache Line Size
B/D/F/Type: 0/3/0/PCI
Address Offset: Ch
Default Value: 00h
Access: RO
Size: 8 bits
7.1.7 MLT—Master Latency Timer
B/D/F/Type: 0/3/0/PCI
Address Offset: Dh
Default Value: 00h
Access: RO
Size: 8 bits
7.1.8 HTYPE—Header Type
B/D/F/Type: 0/3/0/PCI
Address Offset: Eh
Default Value: 80h
Access: RO
Size: 8 bits
Bit Access
Default
Value
Description
7:0 RO 00h Cache Line Size (CLS): Not implemented, hardwired to 0.
Bit Access
Default
Value
Description
7:0 RO 00h Master Latency Timer (MLT): Not implemented, hardwired to 0.
Bit Access
Default
Value
Description
7RO 1b
Multi-Function Device (MFD): Indicates the HECI host controller is part of a
multi-function device.
6:0 RO 0000000b
Header Layout (HL): Indicates that the HECI host controller uses a target
device layout.
Datasheet 195
Intel Manageability Engine Subsystem PCI (D3:F0,F3)
7.1.9 HECI_MBAR—HECI MMIO Base Address
B/D/F/Type: 0/3/0/PCI
Address Offset: 10–17h
Default Value: 0000000000000004h
Access: RO, RW
Size: 64 bits
7.1.10 SS—Sub System Identifiers
B/D/F/Type: 0/3/0/PCI
Address Offset: 2C–2Fh
Default Value: 00000000h
Access: RWO
Size: 32 bits
Bit Access
Default
Value
Description
63:4 RW
0000000
0000000
0h
Base Address (BA): Base address of register memory space.
3RO0bPrefetchable (PF): Indicates that this range is not pre-fetchable
2:1 RO 10b
Type (TP): Indicates that this range can be mapped anywhere in 64-bit address
space.
0RO0b
Resource Type Indicator (RTE): Indicates a request for register memory
space.
Bit Access
Default
Value
Description
31:16 RWO 0000h
Subsystem ID (SSID): Indicates the sub-system identifier. This field should be
programmed by BIOS during boot-up. Once written, this register becomes Read
Only. This field can only be cleared by PLTRST#.
15:0 RWO 0000h
Subsystem Vendor ID (SSVID): Indicates the sub-system vendor identifier.
This field should be programmed by BIOS during boot-up. Once written, this
register becomes Read Only. This field can only be cleared by PLTRST#.
PREVIOUS5859606162636465666768697071NEXT