Datasheet 191
Intel Manageability Engine Subsystem PCI (D3:F0,F3)
7 Intel Manageability Engine
Subsystem PCI (D3:F0,F3)
This chapter provides the register descriptions for Device 3 (D3), Functions 0 (F0) and
3 (F3).
7.1 HECI Function in ME Subsystem (D3:F0)
Device 3 contains registers for the Intel Manageability Engine. The table below lists the
PCI configuration registers in order of ascending offset address.
Note: The following sections describe Device 3 configuration registers only.
Table 13. HECI Function in ME Subsystem (D3:F0) Register Address Map
Address
Offset
Symbol Register Name
Default
Value
Access
0–3h ID Identifiers 29E48086h RO
4–5h CMD Command 0000h RO, RW
6–7h STS Device Status 0010h RO
8h RID Revision ID
See register
description
RO
9–Bh CC Class Code 0C8001h RO
Ch CLS Cache Line Size 00h RO
Dh MLT Master Latency Timer 00h RO
Eh HTYPE Header Type 80h RO
10–17h HECI_MBAR HECI MMIO Base Address
0000000000
000004h
RO, RW
2C–2Fh SS Sub System Identifiers 00000000h RWO
34h CAP Capabilities Pointer 50h RO
3C–3Dh INTR Interrupt Information 0100h RO, RW
3Eh MGNT Minimum Grant 00h RO
3Fh MLAT Maximum Latency 00h RO
40–43h HFS Host Firmware Status 00000000h RO
50–51h PID PCI Power Management Capability ID 8C01h RO
52–53h PC PCI Power Management Capabilities C803h RO
54–55h PMCS
PCI Power Management Control And
Status
0008h
RWC, RO,
RW
8C–8Dh MID Message Signaled Interrupt Identifiers 0005h RO
8E–8Fh MC
Message Signaled Interrupt Message
Control
0080h RO, RW
90–93h MA
Message Signaled Interrupt Message
Address
00000000h RW, RO
94–97h MUA
Message Signaled Interrupt Upper
Address (Optional)
00000000h RW
98–99h MD
Message Signaled Interrupt Message
Data
0000h RW
A0h HIDM HECI Interrupt Delivery Mode 00h RW
