Datasheet 185
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.51 VC0RCAP—VC0 Resource Capability
B/D/F/Type: 0/1/0/MMR
Address Offset: 110–113h
Default Value: 00000001h
Access: RO
Size: 32 bits
Bit Access
Default
Value
Description
31:16 RO 0000h Reserved
15 RO 0b
Reject Snoop Transactions (RSNPT):
0 = Transactions with or without the No Snoop bit set within the Transaction
Layer Packet header are allowed on this VC.
1 = When Set, any transaction for which the No Snoop attribute is applicable but
is not Set within the TLP Header will be rejected as an Unsupported Request.
14:8 RO 0000h Reserved
7:0 RO 01h
Port Arbitration Capability: Indicates types of Port Arbitration supported by
the VC resource. This field is valid for all Switch Ports, Root Ports that support
peer-to-peer traffic, and RCRBs, but not for PCI Express Endpoint devices or
Root Ports that do not support peer to peer traffic.
Each bit location within this field corresponds to a Port Arbitration Capability
defined below. When more than one bit in this field is Set, it indicates that the
VC resource can be configured to provide different arbitration services.
Software selects among these capabilities by writing to the Port Arbitration
Select field (see below).
Defined bit positions are:
Bit[0] = Default = 01b; Non-configurable hardware-fixed arbitration
scheme, e.g., Round Robin (RR)
Bit[1] = Weighted Round Robin (WRR) arbitration with 32 phases
Bit[2] = WRR arbitration with 64 phases
Bit[3] = WRR arbitration with 128 phases
Bit[4] = Time-based WRR with 128 phases
Bit[5] = WRR arbitration with 256 phases
Bits[6:7] = Reserved
MCH default indicates "Non-configurable hardware-fixed arbitration scheme".
