Host-Primary PCI Express* Bridge Registers (D1:F0)

178 Datasheet

6.42 SLOTCTL—Slot Control

B/D/F/Type: 0/1/0/PCI

Address Offset: B8–B9h

Default Value: 0000h

Access: RO, RW

Size: 16 bits

PCI Express Slot related registers.

4RO0b

Power Indicator Present (PIP): When set to 1b, this bit indicates that a

Power Indicator is electrically controlled by the chassis for this slot.

3RO0b

Attention Indicator Present (AIP): When set to 1b, this bit indicates that an

Attention Indicator is electrically controlled by the chassis.

2RO0b

MRL Sensor Present (MSP): When set to 1b, this bit indicates that an MRL

Sensor is implemented on the chassis for this slot.

1RO0b

Power Controller Present (PCP): When set to 1b, this bit indicates that a

software programmable Power Controller is implemented for this slot/adapter

(depending on form factor).

0RO0b

Attention Button Present (ABP): When set to 1b, this bit indicates that an

Attention Button for this slot is electrically controlled by the chassis.

Bit Access

Default

Value

Description

Bit Access

Default

Value

Description

15:13 RO 000b Reserved

12 RO 0b

Data Link Layer State Changed Enable (DLLSCE): If the Data Link Layer

Link Active capability is implemented, when set to 1b, this field enables software

notification when Data Link Layer Link Active field is changed.

If the Data Link Layer Link Active capability is not implemented, this bit is

permitted to be read-only with a value of 0b.

11 RO 0b

Electromechanical Interlock Control (EIC): If an Electromechanical

Interlock is implemented, a write of 1b to this field causes the state of the

interlock to toggle. A write of 0b to this field has no effect. A read to this register

always returns a 0.

10 RO 0b

Power Controller Control (PCC): If a Power Controller is implemented, this

field when written sets the power state of the slot per the defined encodings.

Reads of this field must reflect the value from the latest write, unless software

issues a write without waiting for the previous command to complete in which

case the read value is undefined.

Depending on the form factor, the power is turned on/off either to the slot or

within the adapter. Note that in some cases the power controller may

autonomously remove slot power or not respond to a power-up request based on

a detected fault condition, independent of the Power Controller Control setting.

The defined encodings are:

0 = Power On

1 = Power Off

If the Power Controller Implemented field in the Slot Capabilities register is set

to 0b, then writes to this field have no effect and the read value of this field is

undefined.

Datasheet 179

Host-Primary PCI Express* Bridge Registers (D1:F0)

9:8 RO 00b

Power Indicator Control (PIC): If a Power Indicator is implemented, writes to

this field set the Power Indicator to the written state. Reads of this field must

reflect the value from the latest write, unless software issues a write without

waiting for the previous command to complete in which case the read value is

undefined.

00 = Reserved

01 = On

10 = Blink

11 = Off

If the Power Indicator Present bit in the Slot Capabilities register is 0b, this field

is permitted to be read-only with a value of 00b.

7:6 RO 00b

Attention Indicator Control (AIC): If an Attention Indicator is implemented,

writes to this field set the Attention Indicator to the written state.

Reads of this field must reflect the value from the latest write, unless software

issues a write without waiting for the previous command to complete in which

case the read value is undefined. If the indicator is electrically controlled by

chassis, the indicator is controlled directly by the downstream port through

implementation specific mechanisms.

00 = Reserved

01 = On

10 = Blink

11 = Off

If the Attention Indicator Present bit in the Slot Capabilities register is 0b, this

field is permitted to be read only with a value of 00b.

5:4 RO 00b Reserved

3RW0b

Presence Detect Changed Enable (PDCE): When set to 1b, this bit enables

software notification on a presence detect changed event.

2RO0b

MRL Sensor Changed Enable (MSCE): When set to 1b, this bit enables

software notification on a MRL sensor changed event.

Default value of this field is 0b. If the MRL Sensor Present field in the Slot

Capabilities register is set to 0b, this bit is permitted to be read-only with a value

of 0b.

1RO0b

Power Fault Detected Enable (PFDE): When set to 1b, this bit enables

software notification on a power fault event.

Default value of this field is 0b. If Power Fault detection is not supported, this bit

is permitted to be read-only with a value of 0b

0RO0b

Button Pressed Enable (ABPE): When set to 1b, this bit enables software

notification on an attention button pressed event.

Bit Access

Default

Value

Description

Host-Primary PCI Express* Bridge Registers (D1:F0)

180 Datasheet

6.43 SLOTSTS—Slot Status

B/D/F/Type: 0/1/0/PCI

Address Offset: BA–BBh

Default Value: 0000h

Access: RO, RWC

Size: 16 bits

PCI Express Slot related registers.

Bit Access

Default

Value

Description

15:7 RO 0000000b Reserved

6RO 0b

Presence Detect State (PDS): This bit indicates the presence of an adapter

in the slot, reflected by the logical "OR" of the Physical Layer in-band presence

detect mechanism and, if present, any out-of-band presence detect

mechanism defined for the slot's corresponding form factor. Note that the in-

band presence detect mechanism requires that power be applied to an adapter

for its presence to be detected.

0 = Slot Empty

1 = Card Present in Slot

This register must be implemented on all Downstream Ports that implement

slots. For Downstream Ports not connected to slots (where the Slot

Implemented bit of the PCI Express Capabilities Register is 0b), this bit must

return 1b.

5:4 RO 00b Reserved

3RWC 0b

Detect Changed (PDC): This bit is set when the value reported in Presence

Detect State is changed.

2RO 0b

MRL Sensor Changed (MSC): If an MRL sensor is implemented, this bit is set

when a MRL Sensor state change is detected. If an MRL sensor is not

implemented, this bit must not be set.

1RO 0b

Power Fault Detected (PFD): If a Power Controller that supports power fault

detection is implemented, this bit is set when the Power Controller detects a

power fault at this slot. Note that, depending on hardware capability, it is

possible that a power fault can be detected at any time, independent of the

Power Controller Control setting or the occupancy of the slot. If power fault

detection is not supported, this bit must not be set.

0RO 0b

Attention Button Pressed (ABP): If an Attention Button is implemented,

this bit is set when the attention button is pressed. If an Attention Button is not

supported, this bit must not be set.

Part #	31761
Description
Category	RELAY
Availability	In Stock
Qty	1

31761

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