Host-Primary PCI Express* Bridge Registers (D1:F0)

154 Datasheet

6.12 IOBASE1—I/O Base Address

B/D/F/Type: 0/1/0/PCI

Address Offset: 1Ch

Default Value: F0h

Access: RO, RW

Size: 8 bits

This register controls the processor to PCI Express I/O access routing based on the

following formula:

IO_BASE ≤ address ≤ IO_LIMIT

Only upper 4 bits are programmable. For the purpose of address decode address bits

A[11:0] are treated as 0. Thus the bottom of the defined I/O address range will be

aligned to a 4 KB boundary.

6.13 IOLIMIT1—I/O Limit Address

B/D/F/Type: 0/1/0/PCI

Address Offset: 1Dh

Default Value: 00h

Access: RW, RO

Size: 8 bits

This register controls the processor to PCI Express I/O access routing based on the

following formula:

IO_BASE ≤ address ≤ IO_LIMIT

Only upper 4 bits are programmable. For the purpose of address decode, address bits

A[11:0] are assumed to be FFFh. Thus, the top of the defined I/O address range will be

at the top of a 4 KB aligned address block.

Bit Access

Default

Value

Description

7:4 RW Fh

I/O Address Base (IOBASE): Corresponds to A[15:12] of the I/O addresses

passed by bridge 1 to PCI Express.

3:0 RO 0h Reserved

Bit Access

Default

Value

Description

7:4 RW 0h

I/O Address Limit (IOLIMIT): Corresponds to A[15:12] of the I/O address

limit of device #1. Devices between this upper limit and IOBASE1 will be passed

to the PCI Express hierarchy associated with this device.

3:0 RO 0h Reserved

Datasheet 155

Host-Primary PCI Express* Bridge Registers (D1:F0)

6.14 SSTS1—Secondary Status

B/D/F/Type: 0/1/0/PCI

Address Offset: 1E–1Fh

Default Value: 0000h

Access: RO, RWC

Size: 16 bits

SSTS1 is a 16-bit status register that reports the occurrence of error conditions

associated with secondary side of the "virtual" PCI-PCI bridge embedded within MCH.

Bit Access

Default

Value

Description

15 RWC 0b

Detected Parity Error (DPE): This bit is set by the Secondary Side for a Type 1

Configuration Space header device whenever it receives a Poisoned Transaction

Layer Packet, regardless of the state of the Parity Error Response Enable bit in

the Bridge Control Register.

14 RWC 0b

Received System Error (RSE): This bit is set when the Secondary Side for a

Type 1 configuration space header device receives an ERR_FATAL or

ERR_NONFATAL.

13 RWC 0b

Received Master Abort (RMA): This bit is set when the Secondary Side for

Type 1 Configuration Space Header Device (for requests initiated by the Type 1

Header Device itself) receives a Completion with Unsupported Request

Completion Status.

12 RWC 0b

Received Target Abort (RTA): This bit is set when the Secondary Side for

Type 1 Configuration Space Header Device (for requests initiated by the Type 1

Header Device itself) receives a Completion with Completer Abort Completion

Status.

11 RO 0b

Signaled Target Abort (STA): Not Applicable or Implemented. Hardwired to 0.

The MCH does not generate Target Aborts (the MCH will never complete a

request using the Completer Abort Completion status).

10:9 RO 00b DEVSELB Timing (DEVT): Not Applicable or Implemented. Hardwired to 0.

8RWC0b

Master Data Parity Error (SMDPE): When set indicates that the MCH received

across the link (upstream) a Read Data Completion Poisoned Transaction Layer

Packet (EP=1). This bit can only be set when the Parity Error Enable bit in the

Bridge Control register is set.

7RO0bFast Back-to-Back (FB2B): Not Applicable or Implemented. Hardwired to 0.

6 RO 0b Reserved

5RO0b

66/60 MHz capability (CAP66): Not Applicable or Implemented. Hardwired to

4:0 RO 00h Reserved

Host-Primary PCI Express* Bridge Registers (D1:F0)

156 Datasheet

6.15 MBASE1—Memory Base Address

B/D/F/Type: 0/1/0/PCI

Address Offset: 20–21h

Default Value: FFF0h

Access: RW, RO

Size: 16 bits

This register controls the processor to PCI Express non-prefetchable memory access

routing based on the following formula:

MEMORY_BASE ≤ address ≤ MEMORY_LIMIT

The upper 12 bits of the register are read/write and correspond to the upper 12

address bits A[31:20] of the 32 bit address. The bottom 4 bits of this register are read-

only and return zeroes when read. This register must be initialized by the configuration

software. For the purpose of address decode, address bits A[19:0] are assumed to be

0. Thus, the bottom of the defined memory address range will be aligned to a 1 MB

boundary.

Bit Access

Default

Value

Description

15:4 RW FFFh

Memory Address Base (MBASE): This field corresponds to A[31:20] of the

lower limit of the memory range that will be passed to PCI Express.

3:0 RO 0h Reserved

Part #	31761
Description
Category	RELAY
Availability	In Stock
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31761

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