Datasheet 145

Host-Primary PCI Express* Bridge Registers (D1:F0)

6 Host-Primary PCI Express*

Bridge Registers (D1:F0)

Device 1 contains the controls associated with the PCI Express root port that is the

intended attach point for external graphics. In addition, it also functions as the virtual

PCI-to-PCI bridge. The table below provides an address map of the D1:F0 registers

listed by address offset in ascending order. This chapter provides a detailed bit

description of the registers.

Warning: When reading the PCI Express "conceptual" registers such as this, you may not get a

valid value unless the register value is stable.

The PCI Express* Specification defines two types of reserved bits:

Reserved and Preserved:

• Reserved for future RW implementations; software must preserve value read for

writes to bits.

• Reserved and Zero: Reserved for future R/WC/S implementations; software must

use 0 for writes to bits.

Unless explicitly documented as Reserved and Zero, all bits marked as reserved are

part of the Reserved and Preserved type, which have historically been the typical

definition for Reserved.

Note: Most (if not all) control bits in this device cannot be modified unless the link is down.

Software is required to first disable the link, then program the registers, and then re-

enable the link (which will cause a full-retrain with the new settings).

Table 12. Host-PCI Express Bridge Register Address Map (D1:F0) (Sheet 1 of 3)

Address

Offset

Symbol

Default

Value

Access

0–1h VID1 Vendor Identification 8086h RO

2–3h DID1 Device Identification 29E1h RO

4–5h PCICMD1 PCI Command 0000h RO, RW

6–7h PCISTS1 PCI Status 0010h RO, RWC

8h RID1 Revision Identification 00h RO

9–Bh CC1 Class Code 060400h RO

Ch CL1 Cache Line Size 00h RW

Eh HDR1 Header Type 01h RO

18h PBUSN1 Primary Bus Number 00h RO

19h SBUSN1 Secondary Bus Number 00h RW

1Ah SUBUSN1 Subordinate Bus Number 00h RW

1Ch IOBASE1 I/O Base Address F0h RO, RW

1Dh IOLIMIT1 I/O Limit Address 00h RW, RO

1E–1Fh SSTS1 Secondary Status 0000h RO, RWC

20–21h MBASE1 Memory Base Address FFF0h RW, RO

Host-Primary PCI Express* Bridge Registers (D1:F0)

146 Datasheet

22–23h MLIMIT1 Memory Limit Address 0000h RW, RO

24–25h PMBASE1 Prefetchable Memory Base Address FFF1h RW, RO

26–27h PMLIMIT1 Prefetchable Memory Limit Address 0001h RO, RW

28–2Bh PMBASEU1 Prefetchable Memory Base Address Upper 00000000h RW

2C–2Fh PMLIMITU1 Prefetchable Memory Limit Address Upper 00000000h RW

34h CAPPTR1 Capabilities Pointer 88h RO

3Ch INTRLINE1 Interrupt Line 00h RW

3Dh INTRPIN1 Interrupt Pin 01h RO

3E–3Fh BCTRL1 Bridge Control 0000h RO, RW

80–83h PM_CAPID1 Power Management Capabilities C8039001h RO

84–87h PM_CS1 Power Management Control/Status 00000008h

RO, RW,

RW/P

88–8Bh SS_CAPID Subsystem ID and Vendor ID Capabilities 0000800Dh RO

8C–8Fh SS Subsystem ID and Subsystem Vendor ID 00008086h RWO

90–91h MSI_CAPID Message Signaled Interrupts Capability ID A005h RO

92–93h MC Message Control 0000h RW, RO

94–97h MA Message Address 00000000h RO, RW

98–99h MD Message Data 0000h RW

A0–A1h PE_CAPL PCI Express Capability List 0010h RO

A2–A3h PE_CAP PCI Express Capabilities 0142h RO, RWO

A4–A7h DCAP Device Capabilities 00008000h RO

A8–A9h DCTL Device Control 0000h RW, RO

AA–ABh DSTS Device Status 0000h RO, RWC

AC–AFh LCAP Link Capabilities

020214D02

RO, RWO

B0–B1h LCTL Link Control 0000h

RO, RW,

RW/SC

B2–B3h LSTS Link Status 1000h RWC, RO

B4–B7h SLOTCAP Slot Capabilities 00040000h RWO, RO

B8–B9h SLOTCTL Slot Control 0000h RO, RW

BA–BBh SLOTSTS Slot Status 0000h RO, RWC

BC–BDh RCTL Root Control 0000h RO, RW

C0–C3h RSTS Root Status 00000000h RO, RWC

EC–EFh PELC PCI Express Legacy Control 00000000h RO, RW

100–103h VCECH

Virtual Channel Enhanced Capability

Header

14010002h RO

104–107h PVCCAP1 Port VC Capability Register 1 00000000h RO

108–10Bh PVCCAP2 Port VC Capability Register 2 00000000h RO

Table 12. Host-PCI Express Bridge Register Address Map (D1:F0) (Sheet 2 of 3)

Address

Offset

Symbol

Default

Value

Access

Datasheet 147

Host-Primary PCI Express* Bridge Registers (D1:F0)

6.1 VID1—Vendor Identification

B/D/F/Type: 0/1/0/PCI

Address Offset: 0–1h

Default Value: 8086h

Access: RO

Size: 16 bits

This register combined with the Device Identification register uniquely identify any PCI

device.

10C–

10Dh

PVCCTL Port VC Control 0000h RO, RW

110–113h VC0RCAP VC0 Resource Capability 00000001h RO

114–117h VC0RCTL VC0 Resource Control 800000FFh RO, RW

11A–11Bh VC0RSTS VC0 Resource Status 0002h RO

140–143h RCLDECH Root Complex Link Declaration Enhanced 00010005h RO

144–147h ESD Element Self Description 02000100h RO, RWO

150–153h LE1D Link Entry 1 Description 00000000h RO, RWO

158–15Fh LE1A Link Entry 1 Address

000000000

0000000h

RO, RWO

218–21Fh PESSTS PCI Express Sequence Status

000000000

0000FFFh

Table 12. Host-PCI Express Bridge Register Address Map (D1:F0) (Sheet 3 of 3)

Address

Offset

Symbol

Default

Value

Access

Bit Access

Default

Value

Description

15:0 RO 8086h Vendor Identification (VID1): PCI standard identification for Intel.

Part #	31761
Description
Category	RELAY
Availability	In Stock
Qty	1

31761

Related Items

Technical Document