DRAM Controller Registers (D0:F0)
142 Datasheet
5.3.4 EPLE2D—EP Link Entry 2 Description
B/D/F/Type: 0/0/0/PXPEPBAR
Address Offset: 60–63h
Default Value: 02000002h
Access: RO, RWO
Size: 32 bits
This register provides the first part of a Link Entry which declares an internal link to
another Root Complex Element.
5.3.5 EPLE2A—EP Link Entry 2 Address
B/D/F/Type: 0/0/0/PXPEPBAR
Address Offset: 68–6Fh
Default Value: 0000000000008000h
Access: RO
Size: 64 bits
This register provides the second part of a Link Entry which declares an internal link to
another Root Complex Element.
Bit Access
Default
Value
Description
31:24 RO 02h
Target Port Number (TPN): Specifies the port number associated with the
element targeted by this link entry (PEG0). The target port number is with
respect to the component that contains this element as specified by the target
component ID.
23:16 RWO 00h
Target Component ID (TCID): Identifies the physical or logical component
that is targeted by this link entry. A value of 0 is reserved. Component IDs start
at 1. This value is a mirror of the value in the Component ID field of all elements
in this component.
BIOS Requirement: Must be initialized according to guidelines in the PCI
Express* Isochronous/Virtual Channel Support Hardware Programming
Specification (HPS).
15:2 RO 0000h Reserved
1RO1b
Link Type (LTYP): Indicates that the link points to configuration space of the
integrated device which controls the root port for PEG0.
The link address specifies the configuration address (segment, bus, device,
function) of the target root port.
0RWO0b
Link Valid (LV):
0 = Link Entry is not valid and will be ignored.
1 = Link Entry specifies a valid link.
Bit Access
Default
Value
Description
63:28 RO
0000000
00h
Reserved
27:20 RO 00h Bus Number (BUSN):
19:15 RO 00001b
Device Number (DEVN): Target for this link is PCI Express port PEG0
(Device1).
14:12 RO 000b Function Number (FUNN):
11:0 RO 000h Reserved
