DRAM Controller Registers (D0:F0)

130 Datasheet

5.2.44 TSC1—Thermal Sensor Control 1

B/D/F/Type: 0/0/0/MCHBAR

Address Offset: CD8h

Default Value: 00h

Access: RW/L, RW, RS/WC

Size: 8 bits

This register controls the operation of the thermal sensor.

Bits 7:1 of this register are reset to their defaults by MPWROK.

Bit 0 is reset to it's default by PLTRST#.

Bit Access

Default

Value

Description

7RW/L0b

Thermal Sensor Enable (TSE): This bit enables power to the thermal sensor.

Lockable via TCO bit [7].

0 = Disabled

1 = Enabled

6RW0b

Analog Hysteresis Control (AHC): This bit enables the analog hysteresis

control to the thermal sensor. When enabled, about 1 degree of hysteresis is

applied. This bit should normally be off in thermometer mode since the

thermometer mode of the thermal sensor defeats the usefulness of analog

hysteresis.

0 = Hysteresis disabled

1 = Analog hysteresis enabled.

5:2 RW 0000b

Digital Hysteresis Amount (DHA): This bit determines whether no offset, 1

LSB, 2... 15 is used for hysteresis for the trip points.

0000 = Digital hysteresis disabled, no offset added to trip temperature

0001 = Offset is 1 LSB added to each trip temperature when tripped

...

0110 = ~3.0 °C (Recommended setting)

...

1110 = Added to each trip temperature when tripped

1111 = Added to each trip temperature when tripped

1RW/L0b

Thermal Sensor Comparator Select (TSCS): This bit multiplexes between

the two analog comparator outputs. Normally Catastrophic is used. Lockable via

TCO bit [7].

0 = Catastrophic

1 = Hot

Datasheet 131

DRAM Controller Registers (D0:F0)

5.2.45 TSC2—Thermal Sensor Control 2

B/D/F/Type: 0/0/0/MCHBAR

Address Offset: CD9h

Default Value: 00h

Access: RO, RW/L

Size: 8 bits

This register controls the operation of the thermal sensor.

All bits in this register are reset to their defaults by MPWROK.

0RS/WC0b

In Use (IU): Software semaphore bit.

After a full MCH RESET, a read to this bit returns a 0.

After the first read, subsequent reads will return a 1.

A write of a 1 to this bit will reset the next read value to 0.

Writing a 0 to this bit has no effect.

Software can poll this bit until it reads a 0, and will then own the usage of the

thermal sensor.

This bit has no other effect on the hardware, and is only used as a semaphore

among various independent software threads that may need to use the thermal

sensor.

Software that reads this register but does not intend to claim exclusive access of

the thermal sensor must write a one to this bit if it reads a 0, in order to allow

other software threads to claim it.

See also THERM3 bit 7 and IUB, which are independent additional semaphore

bits.

Bit Access

Default

Value

Description

Bit Access

Default

Value

Description

7:4 RO 0h Reserved

DRAM Controller Registers (D0:F0)

132 Datasheet

3:0 RW/L 0h

Thermometer Mode Enable and Rate (TE): If analog thermal sensor mode is

not enabled by setting these bits to 0000b, these bits enable the thermometer

mode functions and set the Thermometer controller rate.

When the Thermometer mode is disabled and TSC1[TSE] =enabled, the analog

sensor mode should be fully functional. In the analog sensor mode, the

Catastrophic trip is functional, and the Hot trip is functional at the offset below

the catastrophic programmed into TSC2[CHO]. The other trip points are not

functional in this mode.

When Thermometer mode is enabled, all the trip points (Catastrophic, Hot,

Aux0) will all operate using the programmed trip points and Thermometer mode

rate.

Note: When disabling the Thermometer mode while thermometer running, the

Thermometer mode controller will finish the current cycle.

Note: During boot, all other thermometer mode registers (except lock bits)

should be programmed appropriately before enabling the Thermometer Mode.

Clocks are memory clocks.

Note: Since prior MCHs counted the thermometer rate in terms of host clocks

rather than memory clocks, the clock count for each setting listed below has

been doubled from what is was on those MCHs. This should make the actual

thermometer rate approximately equivalent across products.

Lockable via TCO bit 7.

0000 = Thermometer mode disabled (i.e, analog sensor mode)

0001 = enabled, 512 clock mode

0010 = enabled, 1024 clock mode (normal Thermometer mode operation),

provides ~3.85 us settling time @ 266 MHz

provides ~3.08 us settling time @ 333 MHz

provides ~2.56 us settling time @ 400 MHz

0011 = enabled, 1536 clock mode

0100 = enabled, 2048 clock mode

0101 = enabled, 3072 clock mode

0110 = enabled, 4096 clock mode

0111 = enabled, 6144 clock mode

provides ~23.1 us settling time @ 266 MHz

provides ~18.5 us settling time @ 333 MHz

provides ~15.4 us settling time @ 400 MHz

all other permutations reserved

1111 = enabled, 4 clock mode (for testing digital logic)

Bit Access

Default

Value

Description

Part #	31761
Description
Category	RELAY
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31761

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